Hitachi, Ltd.

Nobuaki Izuno

Yasuo Kurosu

Koichi Okazawa

Yoshihiro Yokoyama

Tamon Masimo

Kensuke Ooyu

In the bus constitution in an information processing unit for transferring data between a bus-master and bus-slave via a plurality of buses, if a fault occurs in a bus when data is transferred between the bus-master and bus-slave via the buses and the H side fault detection/reporting circuit of the bus-slave or the H side fault detection/processing circuit of the bus-master detects the fault, the data transfer via the bus is stopped and information indicating that the bus is faulty is stored in the bus status information keeping circuit. When the data transfer via the bus ends normally thereafter, the bus selector confirms that the bus is normal from the information of the bus status information keeping circuit and activates the L side bus controller so as to operate the bus and to transfer the data which cannot be transferred due to the bus fault via the bus.

Multiple bus control method and a system thereof

An image data rotating apparatus has an n.times.n dot matrix memory which temporarily stores n.times.n dots of image data supplied from a first image data memory. A row/column selector selects one row or column of the n.times.n dot matrix memory in response to a rotation indicating signal, which selects an integer times 90.degree. as a rotating degree, for example, 0.degree., 90.degree., 180.degree., 270.degree. or the like. The n dots of image data stored in the selected row or colum are re-written by outputting the stored data into a second image data memory, and by inputting another n dots of image data from the first image data memory in the same cycle, and with the repeating of this cycle, all the n.times.n dots of image data stored in the n.times.n dot matrix memory are re-written so that the rotated image data can be retrieved from the second image data memory.

Method and apparatus for rotating dots data

A video signal and a horizontal synchronizing signal provided from a work station are delayed by a plurality of delay circuits having different delay amounts, and phase differences between a sampling clock signal and the delayed signals are detected. A clock generator generates two kinds of clock pulses having opposite phases and the same frequency. A clock selector selects one of the clock pulses as a sampling pulse signal in response to the phase differences. Further, a phase difference between the horizontal synchronizing signal and the video signal is detected so that the phase difference between the horizontal synchronizing signal and the video signal is maintained constant.

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Yokohama, Japan

Nobuaki Izuno