Nippon Telegraph and Telephone Public Corporation

Oki Electric Industry Co., Ltd.

Nobuaki Ieda

Masafumi Tanimoto

Masaru Uesugi

Junichi Murota

Takashi Watanabe

Yoshio Otsuki

Takao Yano

Masato Wada

The buffer circuit is provided with a high sensitivity balanced type flip-flop circuit and a capacative coupling provided by MOS capacitance, and a load drive circuit utilizes bootstrap effect, thus producing complementary signals having a MOS level from a TTL address input signal.

Buffer circuits

Disclosed is a semiconductor integrated circuit device comprising a semiconductor chip including a plurality of elements constituting multi-functional circuits and a control signal generating circuit incorporated within the semiconductor chip. The control signal generating circuit includes a variable resistance element which irreversibly changes its resistivity when a voltage having a magnitude larger than a specific level, is applied. The variable resistance element is connected in series with a fixed resistor which is further connected in parallel to the output electrodes of a field effect transistor. A control signal is applied to the input terminal of the transistor when the resistance of the variable resistance element is intended to change. An output terminal connected to the connection of the serial connected elements indicates logical '1' or '0' depending on whether the variable resistance element is in the high resistivity state or low resistivity state. In the semiconductor integrated circuit, the output of the control signal generating circuit is transmitted to at least one of the multi-functional circuits, so that it is activated or left deactivated.

Integrated circuit having spare parts activated by a high-to-low

A semiconductor switching element comprised by a high resistivity polycrystalline silicon resistor whose resistance irreversibly decreases to a small value at a threshold voltage upon the voltage across the resistor reaching the threshold voltage. A semiconductor memory device is constituted by using the switching element as a memory cell and a semiconductor gate element for controlling the current flowing through the semiconductor switching element.

Irreversible semiconductor switching element and semiconductor memory

A weak signal detecting circuit in which a sensing circuit formed with a flip-flop circuit, and bit lines each having connected thereto a plurality of 1-transistor type memory cells, are interconnected by separation transistors for separating them from each other, and in which power supply transistors are inserted between power sources and the bit lines. When the power supply transistors are turned on, the separation transistors are turned off, so that a signal detection can be performed with little power consumption. Further, in such a case, the bit lines are disconnected from the sensing circuit to thereby enable a high-speed and highly sensitive detecting operation to be stably achieved regardless of the number of memory cells.

Growing community of inventors

Kodaira, Japan

Nobuaki Ieda