Hitachi, Ltd.

Noboru Yamaguchi

Kazuhiko Iwasaki

Yuzo Kita

Yoshimune Hagiwara

Takanori Shimura

Mamoru Sugie

Shigeru Yoshizawa

Tsuneo Funabashi

Junichi Tatezaki

Haruo Koizumi

Koichi Mayama

Kunio Uchiyama

Hideo Nakamura

Kouki Noguchi

Tadahiko Nishimukai

Atsushi Asano

Mitsuru Akizawa

Nobuo Saito

Ryuuji Shibata

Masaru Shibukawa

Kazuo Minorikawa

Tsukasa Sato

A semiconductor memory device includes signal lines, a decoder for decoding an inputted address to output the decoded result to some of the signal lines, a matrixed memory array, a part of which being pre-specified as a compensated area, read out means for reading out data from memory cells in an area specified in accordance with a decode signal on the some signal line, a detector for detecting that the address is related with the compensated area from the decode signal on the some signal lines, the compensated area being pre-related with the some signal lines, and a fixed data outputting circuit for merging predetermined data into a predetermined part of the data read out from the memory cells in accordance with the detection signal to output the merged data. The fixed data outputting circuit is controlled by a control circuit in response to a merge control signal to output the data read out from the memory cells without the merging operation.

Semiconductor memory device with data error compensation

A method of diagnosis of an integrated logic circuit having function blocks, in which a test signal is supplied to the logic circuit; an input signal to and an output signal from at least one of the function blocks are detected by the use of a contactless probing device such as an electron beam probing device or laser beam probing device; simulation is carried out of a normal logic operation of the function block with the detected input signal to provide a simulated output signal; the detected and simulated output signals are compared with each other; and the function block is determined as being normal or abnormal according to the result of the comparison. When the function block includes plural logic elements, the cause of the abnormality may be traced back to a faulty function element by detecting the output of a function element by a contactless probing device, comparing the detected output with a corresponding simulated output and repeating the detection and comparison on other function elements in the function block until the comparison results in coincidence. The function element which receives the signal providing the coincidence as a result of the comparison is determined as the faulty function element.

Method of diagnosing integrated logic circuit

In a microprogram controller by pipeline control which includes a memory for storing a microprogram and a program counter for representing the address of the memory, a microprogram controller includes means for judging whether or not a branch condition of a branch microinstruction is satisfied and means for converting the microinstruction fetched from the memory to a NOP (No Operation) microinstruction from the output of the next step of the memory till the outputs after a plurality of steps by the affirmation output of the judging means. When the affirmation output is obtained from the judging means, part of the memory output is loaded into the program counter and when the negation output is obtained, a value as the sum of a current value plus 1 is loaded into the program counter.

Microprogram controller in which instruction following conditional

Herein disclosed is a method of controlling a microprocessor in accordance with the present invention characterized in that, when the microprocessor for executing a microprogram in accordance with clock cycles .PHI..sub.1 and .PHI..sub.2 receives a command (i.e., STOP signal) for stopping a normal operation from the outside, a freezing signal (i.e., FRZ signal) synchronizing with the clock cycles is generated to bring the operation being executed into a stopped state.

Microprocessor capable of stopping its operation at any cycle time

A data buffer is connected to the first and second processor and the first processor sends a start signal to the second processor, which responds to the start signal by reading data from a data source, such as an input/output device, and then writes the read out data into the data buffer. After conclusion of the writing operation, the second processor sends an end signal to the first processor which is admitted to start sending data stored in the buffer to a host processor after receipt of the start signal. The start signal and the end signal are provided to the second processor and the first processor respectively, after passing through a synchronizing circuit.

Data processing system with an enhanced communication control system

A timing signal generating circuit including a clock source which generates clock pulses of a predetermined period, a binary counter which divides the frequency of the clock pulses from the clock source by n, a logical array which decodes an output of the binary counter and which is composed of semiconductor elements and flip-flop circuits which are set or reset by outputs of the logical array in response to the clock pulses from the clock source with the outputs of the flip-flop circuits being used as timing signals.

Timing signal generating circuit

In a memory device which has a plurality of recirculating type storage loops and in which information of the same addresses of the respective storage loops can be read and written in parallel, a memory device wherein information representing whether or not the corresponding storage loop is a bad or defective loop is written in a specified address of each of the storage loops.

Memory device with circulating storage loops

In a system comprising a memory, an input/output control device, a direct memory access controller and a data bus, the transfer of data between the memory and the input/output control device via the data bus by means of said direct memory access controller during the period of direct memory access mode is effected by controlling the data transfer direction on a data bus so that a control signal for determining the direction of transferring the data by said data bus is recognized in an inverted manner at the memory or the input/output control device only during the period of a data transfer cycle in the direct memory access mode.

Growing community of inventors

Higashiyamato, Japan

Noboru Yamaguchi