Sanyo Electric Co., Ltd.

Tokyo Sanyo Electric Co.

Noboru Usui

Kanji Tanaka

Tsutomu Ishikawa

Kazuhisa Ishiguro

Masashi Arai

Ryuichi Ogawa

Eiju Maehara

Junji Sakamoto

Norio Yamashita

Shigehiko Ikeguchi

A method of manufacturing a System In Package (SIP) or Integrated System in Board (ISB) circuit device in which a plurality of circuit elements are covered with and integrally supported by an insulating resin. A user terminal is connected with an ISB server and an ISB mounting factory through a communication network. Specifications to be satisfied by an ISB circuit device desired by a user, such as an external size and terminal information of the ISB and circuit diagram CAD data, for example, are input through the user terminal and transmitted to the ISB server. The ISB server in turn transmits information concerning the due date and cost of the ISB circuit device and also a reliability evaluation result to the user terminal. The ISB server also generates mask data for manufacturing the ISB circuit device based on the input specifications, and transmits the mask data to the ISB mounting factory. The ISB mounting factory, receiving the manufacturing data from the ISB server, manufactures the ISB circuit device and provides the ISB circuit device to the user.

Method of manufacturing circuit device using a communication network

An improved FMX sterophonic broadcast receiver provided with countermeasures against transient noises, which includes a level detection circuit for detecting level of a detected stereo difference signal, and a level control circuit for controlling level of an expanded stereo difference signal according to an output signal of the level detection circuit. By the above arrangement of the present invention, since it is so arranged to cause the level control circuit to function when the degree of modulation becomes large so as to control the level of the stereo difference signal to be low, a level difference is produced between the stereo sum signal and the stereo difference signal for deterioration of the stereo separation degree upon matrixing at a matrix circuit for reduction of noises accordingly.

FMX stereophonic broadcast receiver

An FMX stereophonic receiver receives an FMX stereophonic broadcast signal which includes a stereo sum signal, an uncompressed stereo difference signal, and a compressed stereo difference signal which is formed by modulating the uncompressed stereo difference signal by a quadrature modulation and being compressed. The FMX stereophonic receiver includes an FM detector for producing an FM detection signal including a stereo pilot signal, a PLL circuit for producing a signal which is in a synchronized relationship with the stereo pilot signal included in the FM detection signal, a synchronous detection circuit for receiving the FM detection signal and for producing the uncompressed stereo difference signal in accordance with the signal produced from the PLL circuit, a quadrature detection circuit for receiving the FM detection signal and for producing the compressed stereo difference signal in accordance with the signal produced from the PLL circuit, and a phase shifting means for shifting the phase of at least one of the FM detection signal applied to the PLL circuit and the FM detection signal applied to the detection circuits so as to correct the phase difference between the synchronous detection signal and the signal to be detected.

FMX stereophonic receiver

An FM/FMX stereophonic receiver is capable of receiving an FM or an FMX stereophonic broadcast signal. The FM stereophonic broadcast signal includes a stereo sum signal and stereo difference signal, whereas the FMX stereophonic broadcast signal further includes a compressed stereo difference signal and an FMX ID signal indicating the FMX stereophonic broadcast signal. The FM/FMX stereophonic receiver has a stereo demodulator for receiving said broadcast signal and for producing left and right stereo signals, a detector for detecting the field strength of the receiving signal, and a noise reducer, which may be a circuit for changing the mode from stereophonic mode to monaural mode or a high cut circuit for attenuating the signals of high frequency region, for reducing noise signals contained in the left and right stereo signals. The FM/FMX stereophonic receiver further has a detector for detecting the FMX ID signal and a disabling circuit for disabling the noise reducer when the FMX ID signal is detected by the detector. Instead of the disabling circuit, a timing control circuit may be provided for changing the timing at which the noise reducer starts to activate in response to the detection of the FMX ID signal.

FM/FMX stereophonic receiver

A demodulating circuit is capable of controlling stereo separation as a function of an electric field strength. An intermediate frequency signal not limited obtained from an intermediate frequency circuit is utilized as a signal representative of the level associated with the electric field strength. Stereo separation is discontinuously controlled as a function of the signal representative of the electric field strength. The separation is maintained in the possible maximum value in the region exceeding a predetermined value of the electric field strength but is abruptly decreased to a given value between a stereo state and a monaural state from the above described maximum value (stereo state) when the electric field strength becomes smaller than the above described predetermined value and the separation is changed as a function of the electric field strength in the region smaller than the above described value of the electric field strength.

Demodulating circuit for controlling stereo separation

A frequency synthesizer for use in a transmitter/receiver, comprising a voltage controlled oscillator, a programmable frequency divider for dividing the frequency of the output from the voltage controlled oscillator, a reference oscillator, a reference counter for dividing the frequency of the output from the reference oscillator, a phase detector for phase detecting the frequencies of the reference counter and the frequency divider for providing a control voltage to said voltage controlled oscillator, a transmitting/receiving mode selection circuit for selectively controlling the programmable frequency divider such that the frequency division rate thereof is different in the transmitting and receiving modes, a channel designating circuit, a first output terminal for withdrawing an output by mixing the output from the voltage controlled oscillator with the output from the reference oscillator, and a second output terminal for directly withdrawing the output from the voltage controlled oscillator, said transmitting/receiving mode selection circuit comprising a transmitter/receiver selection switch, and full adder means or a read only memory for storing in advance information concerning the frequency division rate of the frequency divider based on the output from the transmitter/receiver selection switch and the output from the channel designating circuit.

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Oota, Japan

Noboru Usui