Kabushiki Kaisha Toshiba

Noboru Tanabe

Shigeru Oyanagi

Masaru Nakamura

Katsuji Kaminishi

Yoshinori Kuno

Kazunori Sekido

Koichi Hasebe

Shinichi Baba

A communication control device includes a plurality of receive buffers each storing therein received information that corresponds to all or a part of a received message or an argument of a receive function, a hash-value generating unit that generates a hash value from a receive key contained in the received message in accordance with a hash-value generation rule, a storing unit that stores the received information in a selected one of the receive buffers corresponding to the hash value, and an output unit that outputs the received information from one of the receive buffers corresponding to the hash value in response to a transmission request from a receiving unit that performs a receiving operation by determining a matching based on a receive key specified by the receive function.

Communication control device, information processing device and computer program product

A memory access control device capable of reducing the cache miss penalty and taking an advantage of the DRAM with a high transmission bandwidth. In this device, a high speed memory for storing block data read from the memory device is provided, Then, when an access request is received from the master device, data requested by the access request is returned from the high speed memory to the master device whenever the data requested by the access request are contained in the block data stored in the high speed memory. Otherwise new block data of a variable block length to be stored in the high speed memory is read from the memory device according to the access request received from the master device. The block data includes prefetch data which have a possibility for being requested by a next access request from the master device. The device may include an access continuity judging unit for judging an access continuity for memory accesses made by the master device such that the read out block length of the new block data is controlled according to the access continuity.

Memory access control device with prefetch and read out block length

An optical interconnection capable of realizing smooth data transmissions among micro-processors provided on a plurality of processor boards. An optical interconnection includes: a series of optical devices, provided on the processor boards separately, each optical device on each processor board being connected with the processor elements provided on that processor board and including a multiplicity of optical element cells for intercepting light signals from a first side of the optical device, transmitting intercepted light signals to a second side of the optical device, and emitting light signals to the second side of the optical device; and an optical path for optically connecting the optical devices such that light signals coming from the second side of one optical device are intercepted at the first side of another optical device.

Optical interconnection suitable for highly parallel computer system

A portable display device capable of presenting a document in an easy to read format, in which a simultaneous display of different parts of the document in reasonable sizes can be made, by a simple operation of the device. The display device comprises a document memory for storing documents to be displayed, at least two display screens for displaying the documents stored in the document memory means, and a display control unit for controlling displays of the documents on the display screens to be in a linked mode in which the displays on the display screens are linked together and in a separate mode in which the displays on the display screens are independent from each other.

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Kanagawa, Japan

Noboru Tanabe