Sharp Kabushiki Kaisha Corporation

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Sharp Semiconductor Innovation Corporation

Noboru Takeuchi

Takuji Tanigami

Fujio Masuoka

Takashi Yokoyama

Tetsuo Endoh

Takahiro Inoue

Yoshifumi Masuda

Daiki Naruse

Toshiya Fujiyama

Hirokazu Sasabe

Mitsutoshi Okami

Yoshihisa Wada

Shinji Horii

Satoru Yamagata

Yoshiji Takamura

Kazuo Ohtsubo

Kazushi Kinoshita

Kota Sato

A detection device according to an aspect of the invention, includes: a housing including an air intake port and an air discharge port; a platelike member having a first air ventilation port and a second air ventilation port, the platelike member being provided inside the housing; a first sensor provided on an air intake port side of the first air ventilation port on a front face of the platelike member; and a second sensor provided between the first air ventilation port and the second air ventilation port on a rear face of the platelike member.

Detection device and electronic apparatus

A detection mechanism includes a light source disposed on a substrate, a condensing lens disposed between the substrate and light emitted from the light source, and a photodetector disposed on the substrate and under the condensing lens.

Particle detection sensor and particle detector

A particulate detection sensor that detects concentration of a particulate in a fluid includes a light emitting element, a SPAD array light detecting unit, and a signal processing unit. The signal processing unit calculates the concentration of the particulate based on a first pulse count value in a lighting period and a second pulse count value in a lighting-off period.

Particulate detection sensor, dust sensor, air conditioning device, and control method of particulate detection sensor

A solid-state image capturing apparatus includes a pixel array in which a plurality of pixels are arranged in a matrix, where each of the pixels includes: a photodiode for obtaining a signal charge by a photoelectric conversion of an incident light; and an amplifying transistor for the signal charge obtained at the photodiode, and where the amplifying transistor is configured in such a manner that a gate area of the amplifying transistor is defined to be larger than a gate area of other transistors that configure the pixel.

Image capturing apparatus and electronic information device

A comparing circuit of the present invention includes: a charging and discharging circuit to charge a capacitor with charging current and discharge the capacitor with discharging current alternately in response to a switch of an input pulse signal; a comparator circuit to compare a capacitor-voltage (Csig) of the capacitor with a first threshold voltage (Vth) and the capacitor-voltage (Csig) with a second threshold voltage (Vth), which is higher than the first threshold voltage, to generate a pulse signal responsive to a result of this comparison, and to supply an output-signal generating circuit with the pulse signal to switch a level of an output pulse-signal; and a logical operation circuit to adjust a value of the charging current and a value of the discharging current by generating a signal that is based on the pulse signal and is to adjust the value of the charging current and the value of the discharging current of the charging and discharging circuit and supplying the charging and discharging circuit with the signal thus generated. This configuration makes it possible for the comparing circuit to maintain capability of preventing errors, and at the same time, improve in capability of outputting a pulse having a same period as that of an input pulse having a short pause period.

Comparing circuit and infrared receiver

In a transistor of the invention, at a boundary between gate oxideformed on a silicon substrateof a device formation regionand a device isolation filmadjoining the gate oxide, a thickness D' of the gate electrodeis set larger than a uniform thickness D of the gate electrodeon the gate oxide. A height difference A between a surface of the gate oxideand a surface of the device isolation film, a width B of a step portionof the device isolation film, and the thickness D of the gate electrodein its uniform-thickness portion satisfy relationships that D&#x3e;B and A/D+(1&#x2212;(B/D))&#x3e;1. By ion implantation via the gate electrodeand the gate oxide, an impurity is added into a surface portion of the silicon substrateat an end portionof the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substratein the electrode uniform portionof the device formation region. The transistor can be prevented from occurrence of the inverse narrow channel effect and kink characteristics, thus being suitable for scale-down of LSIs, and yet can be manufactured with less steps.

Transistor and transistor manufacturing method

A comparator circuit of the present invention includes a comparator section and a current buffer circuit. In a normal mode, a standby current outputted from the comparator section is amplified by a predetermined times at the current buffer circuit. On the other hand, the standby current is not amplified in a standby mode.

Comparator and infrared remote control receiver

The present invention provides a semiconductor memory device having one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein each of the memory cells is formed of a charge storage layer, a control gate and an impurity diffusion layer of a second conductivity type which is formed in a portion of the protruding semiconductor layer and the plurality of memory cells is aligned to at least a predetermined direction, and the control gates of the plurality of memory cells is aligned to the predetermined direction are placed so as to be separated from each other.

Semiconductor memory device and manufacturing method for the same

A carrier detecting circuit which generates a carrier detection level by integral action based on a reception signal and detects using the carrier detection level whether a carrier exists is disclosed and includes an integration capacitor that is charged and discharged using a difference current between a current charged from a charging circuit and a current discharged to a discharging circuit, where the charging circuit and the discharging circuit are provided in an integrator which performs the integral action.

Carrier detecting circuit and infrared communication device using same

A method for evaluating a plane orientation dependence of a semiconductor substrate comprises: forming a hard mask on a semiconductor substrate having plane orientation (); anisotropically etching the semiconductor substrate with use of the hard mask as a mask to obtain a surface oriented in a specific crystal orientation; and evaluating a plane orientation dependence of the semiconductor substrate by use of at least a portion of the surface oriented in a specific crystal orientation.

Method for evaluating dependence of properties of semiconductor substrate on plane orientation and semiconductor device using the same

A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

Semiconductor memory and its production process

A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall thereof, a charge storage layer formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, and a control gate formed on the charge storage layer, wherein at least one charge storage layer of said one or more memory cells is partially situated within the recess formed on the sidewall of the island-like semiconductor layer.

Semiconductor memory with gate at least partially located in recess defined in vertically oriented semiconductor layer

A semiconductor memory comprises: a first conductivity type semiconductor substrate and memory cells each constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein the memory cells are disposed in series, and the island-like semiconductor layer on which the memory cells are disposed has cross-sectional areas in a horizontal direction which vary stepwise.

A semiconductor memory comprises: a substrate; and one or more memory cells constituted of at least one island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate and has an insulating film allowing an electric charge to pass at least in a part of a region between the charge storage layer and the island-like semiconductor layer.

Growing community of inventors

Fukuyama, Japan

Noboru Takeuchi