Kabushiki Kaisha Toshiba

Toshiba Infrastructure Systems & Solutions Corporation

Toshiba Ave Co., Ltd.

Noboru Taga

Takashi Seki

Tatsuya Ishikawa

Makoto Tanahashi

Kenichi Matsushita

Shigeru Okita

Toshiyuki Nakanishi

Susumu Komatsu

Takeshi Koyama

Hideki Ono

Kiyoyuki Kawai

Seijiro Yasuki

Yoshimasa Egashira

Tatsuhisa Furukawa

Hideki Oono

Itsuhei Shimizu

Mikihiko Iwaida

According to one embodiment, a signal quality monitoring apparatus includes a signal processor, a comparator and a determiner. The processor obtains output signals from a first transmitter and a second transmitter which are mutually redundant and respectively reproduce digital broadcast signals based on a common origin signal, and generates a first signal based on the output signal from the first transmitter and a second signal based on the output signal from the second transmitter. The comparator compares the first signal and the second signal. The determiner determines a quality of the digital broadcast signal based on a result of the comparison.

Signal quality monitoring apparatus and method

According to one embodiment, a transmission device includes an insertion unit, an allocation unit, a division unit, an IFFT unit, a phase rotation unit, and a transmission unit. The phase rotation unit performs a phase rotation to reduce a PAPR characteristic for each block on which inverse fast Fourier transform has been performed. The transmission unit combines transmission signals, on each of which a phase rotation has been performed by the phase rotation unit, and transmits the combined transmission signal to an external device. In addition, the division unit includes a predetermined band and at least one pilot symbol located outside another of end of this predetermined band on an opposite side of the one end into one block.

Transmission device, reception device, and transmission method

In some embodiments, a wireless communication apparatus may include, but is not limited to, a pilot inserter, a segment divider, a phase rotator, and a first adder. The pilot inserter inserts first and second pilot symbols into a symbol stream. The segment divider divides into a plurality of segments a plurality of subcarriers. Each of the subcarriers is allocated with a respective one of the symbols included in the symbol stream into which the first and second pilot symbols have been inserted. The phase rotator performs, for each segment, a phase rotation to all of the symbols, except for a predetermined one of the first and second pilot symbols, included in the symbol stream. The first adder adds together signals corresponding to the subcarriers included in the plurality of segments to which the phase rotation has been performed by the phase rotator to generate a transmission signal.

Wireless communication apparatus, integrated circuit, transmission method, reception method, and communication method

In some embodiments, a wireless communication apparatus may include, but is not limited to, a segment divider, a reference symbol inserter, a phase rotator, an adder, and a peak-to-average power ratio evaluator. The reference symbol inserter inserts at least one reference symbol having a phase into at least one of the subcarrier segments. The phase rotator performs respective phase rotations to the subcarrier segments, based at least in part on a plurality of different combination patterns, each of the different combination patterns identifying a respective phase rotation to the subcarrier segments. The peak-to-average power ratio evaluator calculates, for each of the plurality of different combination patterns, a peak-to-average power ratio of the transmission signals generated. The peak-to-average power ratio evaluator selects, from the transmission signals, a transmission signal having a smallest peak-to-average power ratio among the plurality of peak-to-average power ratios calculated.

A clock frequency error detecting device includes a system storage portion which stores a synchronization system based on at least one of several types of frame synchronization signals included in a received signal in which a frame synchronization signal in each frame includes a part obtained by shifting of a frame synchronization signal of another frame by a symbol by using a predetermined rule; a pattern matching portion which performs pattern matching between the received signal and the synchronization system; a symbol counter which outputs a symbol number; a timing detection portion which detects the frame synchronization signal of each frame based on a pattern matching processing result and to output the symbol number at the detection timing; and a frequency error detection portion which detects a change of the symbol number and to detect a clock frequency error of the symbol period based on the detection.

Clock frequency error detecting device

In an OFDM reception apparatus, a Fourier transform unit segments a time-domain signal in an OFDM signal in accordance with a segmenting window signal and converts the time-domain signal into a frequency-domain signal. A first signal extraction unit extracts pilot signals periodically arranged in a frequency direction and in a time direction from an output from the Fourier transform unit. A second signal extraction unit extracts differential reference signals from an output from the Fourier transform unit. A delay profile detection unit performs delay profile detection using the output from the second signal extraction unit, and performs delay profile detection on the output from the first signal extraction unit within a range limited on the basis of a result of the detection. A synchronous reproduction unit generates the segmenting window signal using an output from the delay profile detection unit.

OFDM reception apparatus

An apparatus for receiving an OFDM modulated signal includes: an A/D converter converting the received signal to a digital signal; a quadrature demodulator performing quadrature detection of the digital signal and converting the digital signal to a base-band signal; an FFT circuit transforming the base-band signal to a signal of a frequency domain by performing a fast Fourier transformation; an equalizer equalizing the signal of the frequency domain and obtaining demodulated data; an error correcting circuit performing error correction and decoding the demodulated data obtained by the equalizer; an interference detector detecting a receiving quality for each predetermined frequency band from the demodulated data; and a synchronous sequencer assigning weights to the base-band signal and the signal of the frequency domain based on the receiving quality data, and reproducing a timing synchronized signal and a clock pulse required for the demodulation.

OFDM receiving apparatus and method of demodulation in OFDM receiving apparatus

Automatic gain control method and its system

A phase detection circuit detects a phase of a phase detection signal output from a complex multiplication circuit. A frequency error detection circuit detects a frequency error of a phase-detected signal, with the first frequency error detection characteristic in which a first frequency domain is defined as a detection range. An average circuit converts a signal having the detected frequency error into a signal having a second frequency error detection characteristic in which a second frequency domain other than the first frequency domain is defined as a detection range. After the average circuit calculates an average of frequency error signals for each period of time, it converts an average signal into a signal having the original first frequency error detection characteristic and outputs it to an AFC loop filter.

AFC circuit of digital demodulation device

A transmission system is disclosed which permits the receiving end to demodulate multi-valued modulated symbols successfully under fading conditions and reduces the amount of transmitted reference data to improve data transmission efficiency. At the transmitting end, a multiplexing section, a modulating section, and a transmitting section are provided. In transmitting an OFDM transmission frame, null symbols and reference symbols are placed in the beginning portion of the frame and QPSK symbols are placed in an information symbol data region in the frame with equal spacings in time and frequency. At the receiving end, a receiving section, a demodulation section, an equalizing section, and a demultiplexing section are provided. An error detector detects amplitude and phase errors of each carrier from the reference symbols, and a variation detector detects variations in the amplitude and phase of a received signal from the QPSK symbols. The carrier amplitude and phase errors are corrected by a correction information producing section on the amplitude and phase variations of the received signal detected by the variation detector to produce correction information. The equalizing section equalizes the demodulated symbol data according to the correction information.

Orthogonal frequency division multiplexing transmission system and

This invention improves the frequency acquisition range and the resistance to multipath interference. In a digital signal transmission system using OFDM, on the transmission side, some or all of a plurality of equidistant carrier positions are treated as reference carrier positions. The actual transmitted carriers are arranged in a predetermined pattern non-equidistant to the frequency carrier positions to form an OFDM symbol. This OFDM symbol is periodically transmitted as frequency reference symbols. On the reception side, the carrier arrangement pattern of the frequency reference symbols is detected, a carrier frequency offset is detected from the detected pattern offset, and the carrier frequency is compensated based on the frequency offset.

OFDM transmission/reception system and transmitting/receiving apparatus

AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is valid or not through a detection of an absolute sample value of the symbol intermediate timing so as to result a second validity signal, and valid frequency error extractor for extracting the frequency error signal as a frequency control signal for controlling the oscillation frequency of the local oscillator when the frequency error signal has been proved to be valid by the first and the second validity signals.

AFC circuit for QPSK demodulator

A QPSK modulated wave is inputted to an in-phase detector and an orthogonal detector. The detected components are converted to substantially a base band, and each component is digital-converted by A/D converters. Each digital component is spectrum-shaped by digital LPFs. The outputs of digital LPFs are inputted to a complex multiplier and calculated by use of first and second reproduction carriers and expressed as first and second calculation outputs, and inputted to a phase detector. The phase detector obtains phase difference data between the phase expressed by the first and second calculation outputs and a predetermined phase and quadrant data of the phase. The phase difference data is used for a PLL. The phase difference data is is inputted to a frequency error detection circuit detecting a frequency error. The frequency error output is smoothed by a filter of an AFC loop, and used as a control signal controlling the oscillation frequency of the local oscillation unit. If the frequency error is large, the frequency error detection circuit controls the AFC loop to be in an operation state and the PLL loop and the PLL loop to be in a fixed state. If the frequency error is small, the frequency error detection circuit contains the control state of the AFC loop and switches the PLL loop to be the operation state.

Demodulator for digitally modulated wave

A receiver for selectively receiving high frequency signals from analog modulated signals and digital modulated signals. The receiver has an intermediate frequency signal circuit for selecting a desired channel of the high frequency signals and for frequency-converting the high frequency signal of the selected channel into an intermediate frequency signal, a demodulator for demodulating the intermediate frequency signal, which is adapted to be capable of demodulating modulated signals in a variety of modulation systems, the demodulator including at least a digital section, and a controller for controlling the demodulator to be able to discriminate between the analog modulated signals and the digital modulated signals, based on a demodulated signal output from the digital section of the demodulator and to be switched into a demodulation mode suited for modulation system of the selected channel of the high frequency signals.

Receiver adaptively operable for multiple signal transmission systems

A digital phase locked loop which incorporates a phase comparator which produces a phase deviation signal having a sinusoidal phase comparison characteristic rather than a sawtooth phase comparison characteristic in order to avoid aliases.

Growing community of inventors

Kanagawa, Japan

Noboru Taga