Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Noboru Shibata

Tomoharu Tanaka

Tokumasa Hara

Hiroshi Sukegawa

Katsuaki Isobe

Mitsuaki Honma

Hiroshi Maejima

Toshihiro Suzuki

Hironori Uchikawa

Jun Nakai

Toshiki Hisada

Kazunori Kanebako

Kenichi Imamiya

Ken Takeuchi

Yuji Nagai

Taku Kato

Tatsuyuki Matsushita

Takahiro Shimizu

Toru Tanzawa

Koji Hosono

Weihan Wang

Toshifumi Hashimoto

Yasuyuki Matsuda

Takuya Futatsuyama

Hiroto Nakai

Toshio Yamamura

Susumu Fujimura

Kazuaki Isobe

Taira Shibuya

Tadashi Yasufuku

Hideo Kato

Kikuko Sugimae

Koichi Kawai

Katsuya Nishiyama

Masaki Fujiu

Akiyuki Murayama

Kenri Nakai

Makoto Miakashi

Yasukazu Kosaki

Motohiko Fujimatsu

Shinji Saito

Naoki Kobayashi

Tsuneo Inaba

Hiroshi Yao

Hideo Shimizu

Hitoshi Shiga

Naomi Takeda

Yusuke Arayashiki

Taira Iwase

Yoshikazu Takeyama

Daiki Watanabe

Mikio Ogawa

Takafumi Ikeda

Yoshio Mochizuki

Yoshihisa Kondo

Yasuyuki Fukuda

Masatsugu Kojima

Kyosuke Sano

Manabu Sato

Kouichirou Yamaguchi

Kenji Yano

According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

Semiconductor memory with different threshold voltages of memory cells

According to one embodiment, a memory device is configured to execute an efficient read operation is provided. The memory device includes a plurality of memory cells, a word line, and a controller. Each of the memory cells stores first to fifth bit data based on the threshold voltage. The memory cells store a first page to a fifth page respectively corresponding to the first bit data to the fifth bit data. A word line is coupled to the memory cells. A controller executes a read operation for reading data from the memory cells by applying a read voltage to the word line. Numbers of times the controller applies read voltages different from one another to the word line in read operations for the first page to the fifth page are 7, 6, 6, 6, and 6, respectively.

Memory device applying plural different read voltages to a word line in a read operation

In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Semiconductor memory device capable of shortening erase time

A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

Memory system

According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Nonvolatile memory and writing method

According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

Semiconductor memory device

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

Nonvolatile semiconductor memory device which performs improved erase operation

A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

Semiconductor memory

According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2second distributions are separately formed two by two. The circuit then sets 2third distributions for the 2sections.

Semiconductor memory device and method

A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Semiconductor memory system including first and second semiconductor memory chips and a common signal line

A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Nonvolatile memory multilevel cell programming

According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

Semiconductor memory device, memory system, and write method

In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k&#x2264;n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Growing community of inventors

Kawasaki, Japan

Noboru Shibata