Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Nitto-denko Corporation

Renesas Technology Corp.

Noboru Moriuchi

Yoshihiko Okamoto

Fumio Mizuno

Seiichiro Shirai

Masayuki Morita

Toshihiko Tanaka

Yoshiki Yamaguchi

Norio Hasegawa

Tokuo Kure

Yoshifumi Kawamoto

Toru Kaga

Shin-ichiro Kimura

Yutaka Moroishi

Seiichirou Shirai

Makoto Sunakawa

Michirou Kawanishi

Toshihiko Onozuka

Herein disclosed is an exposure technology for a semiconductor integrated circuit device which has a pattern as fine as that of an exposure wavelength. The technology contemplates to improve the resolution characteristics of the pattern by making use of the mutual interference of exposure luminous fluxes.

Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process

Process for fabricating semiconductor integrated circuit device, and

One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.

Manufacturing method or an exposing method for a semiconductor device or

A technique to minimize an increase in the design and manufacture times required for making phase shift masks is provided. The process of the technique involves preparing a hole unit cell comprising one target hole and auxiliary holes located close to the four sides of the target hole, and then laying out on first layout data first hole unit cells 26c.sub.1 -26c.sub.3 arranged in a certain orientation at a first pitch and second hole unit cells 27c.sub.1 -27c.sub.3 arranged in the same orientation at a second pitch, narrower than the first pitch. This process generates data of hole groups, each comprising the target hole and auxiliary holes on a first phase shift mask that is used in forming hole patterns in a resist film coated over the semiconductor substrate.

Method of manufacturing phase shift masks and a method of manufacturing

A method for removing a resist pattern formed on a semiconductor wafer, and a curable pressure-sensitive adhesive, adhesive sheets and an apparatus used for the method. The resist-removing method comprising adhering an adhesive tape on an upper surface of a resist pattern formed on an article and peeling off the resist pattern together with the adhesive tape; the curable pressure-sensitive adhesive constituting the adhesive tape, comprising a pressure-sensitive adhesive polymer containing a non-volatile compound having at least one unsaturated double bond in the molecule and having a good affinity with a resist material to be removed; the adhesive sheet comprising a film substrate having formed thereon the curable pressure-sensitive adhesive; and the resist-removing apparatus comprising a means for press-adhering the adhesive tape, a tape-peeling means, and a substrate-washing means.

Resist removing method, and curable pressure-sensitive adhesive,

Manufacturing method or an exposing method for a semiconductor device

The present invention enables the accuracy of aligning a wafer and a reticle with each other in the exposure step in the manufacture of a semiconductor integrated circuit device to be improved. The portions of a metal film 5 and a resist film 6 which cover an alignment mark 4 on a wafer 1 are removed by a gas assisted etching treatment using a laser beam prior to the execution of an exposure treatment, so as to bare the alignment mark 4. The position detecting light is then applied from an alignment mark position detecting means in a reduction projection exposure unit 11 to the alignment mark 4, the position of the alignment mark 4 being detected on the basis of the light reflected on and scattered from the alignment mark 4.

Alignment method and apparatus

An exposure technology for a semiconductor integrated circuit device which has a pattern as fine as that of an exposure wavelength contemplates to improve the resolution characteristics of the pattern by making use of the mutual interference of exposure luminous fluxes.

A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.

Semiconductor memory device with recessed array region

A semiconductor memory wherein a memory cell region having a plurality of memory cells and has higher altitude from the surface of semiconductor substrate is formed in the recessed part of semiconductor substrate having the recessed part and projected part and a peripheral circuit region which is comparatively low from the surface of semiconductor substrate is formed to the projected part of semiconductor substrate.

Growing community of inventors

Tokyo, Japan

Noboru Moriuchi