Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Mitsubishi Electric Corporation

Noboru Morimoto

Masahiko Fujisawa

Kinya Goto

Daisuke Kodama

Masazumi Matsuura

Akihiko Ohsaki

Masahiro Matsumoto

Atsushi Ishii

Junko Izumitani

Yasutaka Nishioka

Shoichi Fukui

A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.

Semiconductor device having termination region with insulator films having different coefficients of moisture absorption

Semiconductor device having termination region with insulator having low coefficient of moisture absorption

A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.

Semiconductor device and method of manufacture thereof

To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.

Semiconductor device, and manufacturing method thereof

A metal layer ( ), a metallic compound layer ( ) and a metal layer ( ) are stacked in this order when viewed from the side of a first copper interconnect line ( ) and an interlayer insulating film ( ) to constitute a second conductive barrier layer ( ). As the material for the metal layers ( ) and ( ), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line ( ) is conductively connected to the first copper interconnect line ( ) at a contact hole ( ) through the second conductive barrier layer ( ). As the ratio of the volume of the second copper interconnect line ( ) at the region for filling a trench ( ) to the volume of the second copper interconnect line ( ) at the region for filling the contact hole ( ) increases, tensile stress to be concentrated at the contact hole ( ) becomes greater. As a result, a void is likely to be generated in the contact hole ( ). In view of this, in order to improve the adhesion especially between the second copper interconnect line ( ) at the region for filling the contact hole ( ) and the second conductive barrier layer ( ), the metal layer ( ) is provided.

Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer

A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film ( ) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film ( ), the USG film ( ) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film ( ) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film ( ) is cleaned with a cleaning liquid whose etching rate to the FSG film ( ) and etching rate to the USG film ( ) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH OH:H O :H O&equals;1:1:20. The structure shown in FIG. is dipped in the above-mentioned ammonia hydrogen peroxide mixture for 60 seconds to clean the surface of the interlayer dielectric film ( ).

Method of manufacturing semiconductor device and semiconductor device

A second-level wire is formed by a dual damascene process in a insulating film. In an upper surface of the first insulating film a metal film is formed and serves as a first electrode of an MIM-type capacitor. A second insulating films has a structure in which a plurality of insulating films are layered on a second interconnection layer, in this order. In a first insulating film of the plurality of insulating films, a second electrode of the MIM-type capacitor is formed. The second electrode has a first metal film formed on a second insulating film of the plurality of the insulating films and a second metal film is formed on the first metal film. A portion of the second insulating film which is sandwiched between the first electrode and the second electrode of the MIM-type capacitor serves as a capacitor dielectric film of the MIM-type capacitor. In the second insulating film, a third-level wire is formed Thus, a semiconductor device and a method of manufacturing the same are provided such that the MIM-type capacitor is formed together with metal wires with no additional complicated step.

Semiconductor element and MIM-type capacitor formed in different layers of a semiconductor device

A wire width and a wiring space of each of signal wires and ground/power wires are determined to be a wire width W (the minimum wire width) and a wiring space S , respectively. A wire width and a wiring space of the via-hole neighboring region or are determined to be a wire width W (>W ) and a wiring space S (<S ), respectively. The wire widths W and W and the wiring spaces S and S are respectively determined so as to maintain the minimum wiring pitch P. The wiring space S is determined also so as to satisfy &lcub;S /P&gE;0.6&rcub;. Further, the signal wires and the ground/power wires have the same wire thickness of a wire thickness T which allows an aspect ratio (T /W ) to be equal to, or higher than, 2.

Wiring structure for an integrated circuit

Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer

A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film ( ) is deposited to a thickness of 1 Hm over an entire surface of an FSG film ( ), the USG film ( ) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, part of an upper surface of the FSG film ( ) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film ( ) is cleaned with a cleaning liquid whose etching rate to the FSG film ( ) and etching rate to the USG film ( ) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH OH:H O :H O&equals;1:1:20. The structure shown in FIG. is dipped in the above-mentioned ammonia hydrogen peroxide mixture for 60 seconds to clean the surface of the interlayer dielectric film ( ).

Implemented is a method of manufacturing a contact structure having a combination of formation of a buried wiring and that of a low dielectric constant interlayer insulating film in which a connecting hole to be formed in a low dielectric constant interlayer insulating film does not turn into an abnormal shape. A fourth interlayer insulating film is formed on an upper surface of a third interlayer insulating film . Next, patterning for a wiring trench and a connecting hole is carried out into the fourth interlayer insulating film and the third interlayer insulating film , respectively. Then, a pattern of the connecting hole is first formed in a third low dielectric constant interlayer insulating film . Thereafter, a second interlayer insulating film exposed in the pattern is removed and a pattern of the wiring trench is formed in the third interlayer insulating film . Subsequently, second and third low dielectric constant interlayer insulating films and are etched, and the wiring trench and the connecting hole are formed at the same time. Thus, a photoresist can be formed again without the second and third low dielectric constant interlayer insulating films and exposed, and an abnormal shape is generated in the connecting hole with difficulty.

Growing community of inventors

Tokyo, Japan

Noboru Morimoto