Hitachi, Ltd.

Renesas Technology Corp.

Noboru Masuda

Bunichi Fujita

Minoru Yamada

Moritoshi Yasunaga

Takehisa Hayashi

Hiroyuki Itoh

Masayoshi Yagyu

Hirotoshi Tanaka

Kazunori Nakajima

Mitsuo Asai

Seiichi Kawashima

Yasunari Umemoto

Hiroaki Nambu

Makoto Hanawa

Kazuo Kanetani

Kenji Kaneko

Akira Masaki

Kenichi Ishibashi

Takeshi Kusunoki

Kaname Yamasaki

Masakazu Yamamoto

Katsunari Shibata

Hideo Maejima

Akira Yamagiwa

Hiroki Yamashita

Tadaaki Isobe

Toshio Doi

Masamori Kashiyama

Michio Asano

Toshihiro Okabe

Kazumichi Yamamoto

Shuichi Ishii

Hideo Todokoro

Takashi Yano

Shoji Shukuri

Osamu Kagaya

Takeshi Kato

Tatsuya Saito

Kiichi Ueyanagi

Satoshi Masuda

Yasuo Wada

Tadahiko Nishimukai

Nobuo Kotera

Keiichirou Nakanishi

Kazuo Koide

Yoshio Miki

Kiyoshi Kawamoto

Norikazu Hashimoto

Junji Shigeta

Shun Kawabe

Tatsuya Saitoh

Mikio Yamagishi

Ryotaro Kamikawai

Michitaka Yamamoto

Yuzuru Fujita

Sakoh Ishikawa

Yuzo Hirai

Nobutoshi Matsunaga

Masaru Osani

High precision of various feedback systems represented by a PLL circuit and the like is realized. For example, in a charge pump circuit in the PLL circuit, a first to a third PMOS transistors connected in series in three stages are provided between a power source voltage and an output node, and a first to a third NMOS transistors connected in series in three stages are provided between a ground voltage and the output node. And, the second PMOS transistor and the second NMOS transistor are driven ON when establishing conductivity between the power source voltage or the ground voltage and the output node by a first pulse signal, and the first PMOS transistor and the third NMOS transistor are driven OFF when the conductivity is shut down by a second pulse signal. Accordingly, the conduction time can be set by time difference between one edge of the first pulse signal and one edge of the second pulse signal, and therefore, short conduction time can be set, as a result, a charge amount of the charge pump circuit can be controlled precisely.

Semiconductor integrated circuit device

Phase jitter of the hybrid control type PLL circuit in a steady state is reduced. A steady state detection circuit determining whether an output of a phase comparison circuit in the hybrid control type PLL circuit frequently changes is provided, determination that a steady state has not been reached is made if the output of the phase comparison circuit does not change for a while, determination that the steady state has been reached if the output of the phase comparison circuit frequently changes, and based on a result of the determination, a control width of controlling a oscillation frequency of a voltage controlled oscillator circuit by a digital control signal is changed or (and) a frequency of changing an analog control signal is changed. Thereby, a control width of the oscillation frequency by the digital control signal after reaching the steady state can be reduced without damaging convergence before reaching the steady state. Therefore, the phase jitter in the steady state can be reduced.

PLL circuit

The disclosed invention makes mobile terminals physically impossible to use in specific spaces without using radio waves of so high intensity as to affect medical devices and without requiring telephone companies that operate wireless communications systems (WCS) to take special measures. Cooperation of a telephone company on the implementation of making mobile terminals physically impossible to use in specific spaces makes mobile terminals provided by the telephone company easy to use. Pseudo signals of downlink pilot signal in WCS are emitted off the pilot timing in specific spaces. Uplink channel radio waves in cooperative telephone compannies' WCS are relayed and communication path is disconnected if the uplink channel radio waves are for communication of an attribute banned in the space. Communication path can be disconnected without increasing the intensity of radio waves so high. In cooperative telephone compannies' WCS, only the path of communication of an attribute banned in the space is disconnected.

Wireless communication restriction device, repeater and base station

Disclosed is a transmission power control method which enables communications between a base station and a terminal station to be always performed at a high transfer rate by always assuring an uplink communication path between a base station which can transfer a downlink signal most efficiently and a terminal station. Each of terminal stationstoselects a base station which can receive a downlink radio wave with the highest power, and transmits a code for identifying the base station on an uplink signal. When the received power of the uplink radio waves transmitted from the terminal station which has transmitted the code identifying the own station is higher than the threshold value, each of base stationstotransmits a control signal for decreasing the power to the terminal station. When the terminal station sends a code for identifying another station or the power of the uplink radio waves received from the terminal station is lower than the threshold value, a control signal for increasing the power is sent to the terminal station. When even one power control signal for giving instruction to decrease the transmission power exists, each terminal station decreases its transmission power. When there is not the power control signal, each terminal station increases its transmission power.

Transmission power control method of wireless communication terminal and a base station therefore

The present invention relates to a PLL circuit and a voltage controlled oscillator wherein a clock signal jitter caused when the supply voltage fluctuates of which is small can be supplied, and the voltage controlled oscillator is provided with a MOS transistor to one end of which a first power source (Vss) is connected and to the gate electrode of which a control signal for controlling the oscillation frequency is input, an oscillator connected between the other end of the MOS transistor and a second power source (Vdd) and a capacitative element connected to the oscillator in parallel and is further provided with additive control means for minutely controlling the oscillation frequency.

Voltage controlled oscillator and PLL circuit using the same

A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Clocked logic gate circuit

Disclosed herein is a dynamic type circuit which transmits a signal between relatively long-distant circuit blocks lying within a semiconductor integrated circuit chip. A whole signal path thereof comprises a plurality of sections. A section formed by a first type of signal line, which is precharged to a high level and to which a decision as to whether it is driven to a low level according to a signal inputted from a preceding section or it is left in floating state, is made, and a section formed by a second type of signal line, which is precharged to a low level in reverse and to which a decision as to whether it is driven to a high level according to a signal inputted from a preceding section or it is left in a floating state, is made, exist in alternate shifts. The respective sections are respectively connected to preceding-stage sections through MOS transistors for driving signal lines for the sections. MOS transistors for precharge are respectively connected to the signal lines for the respective sections at plural positions where a signal line is partitioned into substantially uniform intervals.

Signal transmission circuit on semiconductor integrated circuit chip

In a dynamic logic circuit, a signal delay time between a low-to-high transition of an input signal and a low-to-high transition of an output signal is reduced, a through current is decreased and a time required for the precharge is reduced. In the dynamic logic circuit a P-channel type MOS transistor (PMOS) has its source electrode connected with a power supply on the side of a high voltage potential Vdd. Its gate electrode receives a clock signal Cs. A logic portion includes N-channel type MOS transistors (NMOS) connected between a drain electrode of the PMOS and a power supply on the side of a low voltage potential Vss. An NMOS is provided between an input signal connected with a NMOS closest to the Vss in the NMOSs and the Vss. A reverse signal of the clock signal Cs is connected with a gate electrode of the NMOS. An input signal is forced to change to a low level at the time of the precharge, thereby a through current is decreased and a time required for the precharge is reduced. Therefore, a signal delay time is reduced.

Dynamic logic circuit and integrated circuit device using the logic circuit

A logic circuit for use as a selector having multiple inputs and high operation speed. The logic circuit includes a first FET having a first electrode connected to a first power supply, a second electrode connected to an output terminal and a third electrode connected to an intermediate control node, and a plurality of logic blocks parallelly connected between the second power supply and the output terminal. Each logic block includes second and third FETs being of a conductivity type opposite to that of the first FET and connected in series between the output terminal and a second power supply. Each logic block also includes a fourth FET being of the same conductivity type as the second and third FETs and having a third electrode connected to the third electrode of the second FET, a first electrode connected to the third electrode of the third FET and a second electrode connected to the intermediate control node. The conduction resistance between the output terminal and the first power supply is reduced and the parasitic capacitance added to the output terminal is also reduced, thereby allowing the logic circuit to be operated at high speed.

Logic circuit

In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

Data-transmitter-receiver

Data transmitter-receiver

An information processing apparatus is composed of an input layer, a hidden layer and an output layer, and performs a computation in terms of neuron models. In the information processing apparatus, a forward network comprising the input layer, the hidden layer and the output layer executes a computation for externally input data to determine the values of outputs therefrom, and a backward network comprising the output layer and the hidden layer executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.

Information processing apparatus

A data processing system having a logic LSI, a plurality of memory LSIs and a circuit which eliminates delays in the time at which data read out form the memory LSIs reach the logic LSI. The circuit includes variable delay circuits for delaying the data signals read out of the memory LSIs. A control circuit start monitors the time when the data read out of the individual memory LSIs arrive at flip-flops which output the data to the logic LSI. The delay times in the variable delay circuits are controlled by the control circuit for the individual memory LSIs so that the times the data read out from the memory LSIs reach the logic LSI may coincide with a predetermined standard time. Thus, the read data from the individual memory LSIs are caused to reach the flip-flops simultaneously.

Data processing system and semiconductor memory suited for the same

Growing community of inventors

Tokorozawa, Japan

Noboru Masuda