Fujitsu Corporation

Noboru Kosugi

Noboru Yokota

Hisayoshi Oba

Munehiro Tahara

Masayoshi Tomita

Tadahiro Saitoh

Kiyokazu Hasegawa

A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S); a mask with a modified pattern is prepared (S); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S).

Semiconductor device having embedded array

A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S ); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S ); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S ); a mask with a modified pattern is prepared (S ); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S ).

A semi-custom integrated circuit comprises a basic cell array comprising a plurality of basic cells aligned in a first direction, the basic cells comprising a transistor unit, a capacitor unit and a resistor unit arranged in a second direction perpendicular to the first direction. The transistor unit is positioned between the capacitor unit and the resistor unit. The transistor unit has a terminal portion for connection of wiring, the capacitor unit having a terminal portion for connection of wiring, the resistor unit having a terminal portion for connection of wiring. The terminal portions of said transistor unit, capacitor unit and resistor unit are aligned along a line.

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Kawasaki, Japan

Noboru Kosugi