Seiko Epson Corporation

Noboru Itomi

Takashi Kumagai

Satoru Kodaira

Junichi Karasawa

Satoru Ito

Shuji Kawaguchi

Kazuhiro Maekawa

Hisanobu Ishiyama

Masahiko Moriguchi

Yosuke Itasaka

Takashi Fujise

Tsuyoshi Tamura

Teppei Higuchi

Kaori Imai

A vibration device includes a base including a semiconductor substrate and a through electrode passing through the portion between a first surface and a second surface of the semiconductor substrate, a vibrator placed at the side facing the first surface, and an external connection terminal provided at the side facing the second surface via an insulating layer. An oscillation circuit that is electrically coupled to the vibrator via the through electrode and generates an oscillation signal by causing the vibrator to oscillate, and an output buffer circuit that outputs a clock signal based on the oscillation signal are placed at the second surface. The clock signal from the output buffer circuit is outputted via the external connection terminal. The through electrode and the external connection terminal are arranged so as not to overlap with each other in a plan view viewed in the direction perpendicular to the first surface.

Vibration device having a through electrode and a clock signal output external connection terminal

An oscillation circuit includes a circuit for oscillation that oscillates a resonator, an output circuit that has a signal, output from the circuit for oscillation, input thereto to thereby output an oscillation signal, a connection terminal to which power is applied, a first wiring that connects from the connection terminal to the output circuit, and a second wiring that is connected to the first wiring through a connection node provided on the first wiring and connects from the connection node to the circuit for oscillation. The circuit for oscillation, the output circuit, the connection terminal, the first wiring, and the second wiring are provided on a semiconductor substrate. The length of a wiring extending from the connection terminal of the first wiring to the connection node is shorter than the length of the second wiring.

Oscillation circuit, oscillator, electronic apparatus and moving object

A circuit device includes an oscillation circuit generating an oscillation signal by oscillating a vibrator, a temperature sensor circuit performing an intermittent operation, a logic circuit performing temperature compensation processing based on an output of the temperature sensor circuit, and a power supply circuit supplying power to the oscillation circuit. The oscillation circuit is disposed in a circuit region, the temperature sensor circuit and the logic circuit are disposed in a circuit region, and the power supply circuit is disposed in a circuit region, which is positioned between the circuit region and the circuit region.

Circuit device and oscillator

A vibration device includes a base including a semiconductor substrate and through electrodes that pass through the portion between first and second surfaces of the semiconductor substrate, and a vibrator fixed to the first surface via an electrically conductive joining member. The following components are placed at the second surface: an oscillation circuit that is electrically coupled to the vibrator via the through electrodes and generates an oscillation signal by causing the vibrator to oscillate, a temperature sensor circuit, a temperature compensation circuit that performs temperature compensation on the oscillation signal, and an output buffer circuit that outputs a clock signal based on the oscillation signal. Dsx&#x3c;Dbx, a distance between the output buffer circuit and one of the through electrodes is Dbx, a distance between the temperature sensor circuit and the other through electrode is Dsx

Vibration device

A semiconductor integrated circuit includes a first MOS transistor, a second MOS transistor, and a P+ region. The first MOS transistor is an NMOS transistor which has a first N-type region and a second N-type region and in which a first power supply voltage is supplied to the first N-type region. The second MOS transistor is an NMOS transistor which has a third N-type region and a fourth N-type region and in which a second power supply voltage higher than the first power supply voltage is supplied to the third N-type region. The P+ region is supplied with the first power supply voltage. In plan view of the semiconductor substrate, the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and the P+ region is located between the first N-type region and the third N-type region.

Semiconductor integrated circuit, electronic device and vehicle

A semiconductor device includes a first high resistance pattern and a second high resistance pattern that are disposed along an X axis and are separated from each other, a coupling pattern that couples the first high resistance pattern and the second high resistance pattern, and a signal wiring disposed at a layer above the first high resistance pattern, the second high resistance pattern, and the coupling pattern. The coupling pattern includes a first portion that overlaps an end portion of the first high resistance pattern in a plan view at the layer above the first high resistance pattern, the coupling pattern includes a second portion that overlaps an end portion of the second high resistance pattern in a plan view at a layer above the second high resistance pattern, and the signal wiring is disposed along a Y axis that intersects the X axis in a plan view between an end of the coupling pattern at the first portion side and an end of the coupling pattern at the second portion side.

Semiconductor device and oscillator

An integrated circuit device includes first to Nth circuit blocks CBto CBN, a first interface region disposed along a fourth side and on the Dside of the first to Nth circuit blocks CBto CBN, and a second interface region disposed along a second side and on the Dside of the first to Nth circuit blocks CBto CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction Dover the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.

Integrated circuit device and electronic instrument

An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit, each of the RAM blocks is disposed along a first direction in which the bitlines extend, each of the memory cells has a short side and a long side, the bitlines are formed along a direction in which the long side of the memory cell extends, and the wordlines are formed along a direction in which the short side of the memory cell extends.

An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.

An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.

An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, wherein the display memory includes a plurality of RAM blocks each of which includes first and second RAM block regions; wherein each of the RAM blocks includes a wordline control circuit which controls a plurality of wordlines provided in each of the first and second RAM block regions; wherein the wordline control circuit is disposed between the first and second RAM block regions; wherein the first and second RAM block regions are disposed along a first direction; and wherein the wordlines extend along the first direction.

In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines. The display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, and a data read control circuit. Each of the RAM blocks is disposed along a first direction X in which the bitlines BL extend. The data read control circuit controls data reading so that data for pixels corresponding to the signal lines is read out by N times reading in one horizontal scan period 1H of the display panel (N is an integer larger than 1).

Growing community of inventors

Nirasaki, Japan

Noboru Itomi