Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Microcomputer Eng. Ltd.

Noboru Horie

Toshinori Watanabe

Yasuo Kominami

Makoto Furihata

Fumihiko Mori

Fumihito Inoue

Tamotsu Nishiyama

Yoshiji Nakajima

Koji Sasaki

Tetsuya Masuishi

Koichi Haruna

Kazuo Hoya

In a case where an electronic circuit having the same function is to be realized by a different device, it is indispensable to prepare circuit diagrams conforming to devices and to utilize them for the job of circuit simulation or chip layout. When the circuit diagrams are to be automatically translated for the above purpose, translation rules become different depending upon the connective relations of an element to be translated, with other elements in the circuit or upon a function performed by the element. The present invention puts the rules into knowledge from the viewpoint of knowledge engineering and utilizes it thereby to realize the intended purpose. It is characterized in that, when a circuit constructed of a first type of elements is to be translated into a circuit constructed of second type of elements different from the first type of elements, appropriate ones among translation rules are automatically selected for the respective first or second type of elements on the basis of determined results based on knowledge groups of connective relations with other elements of the same circuit and are applied to the first or second type of elements.

Method of automatic circuit translation

In order to translate an original circuit consisting of a set of first devices into a target circuit which consists of a set of second devices different from the first devices, and which has the same functions as the original circuit, provision is made of memory means for storing translation rules in the first devices, translation rules in the second devices, and translation rules between the first devices and the second devices, and translation means which successively refers to these translation rules and translates the original circuit data into the target circuit data via steps that translate the original circuit data into a plurality of intermediate data.

Circuit translator

The structure of a circuit which is given basic net data is stored as a pattern, the compliance of the basic net data with the pattern is checked by the separately prepared search function, and upon fulfillment of compliance the pattern is determined to exist within the circuit. The subcircuit to be recognized by elements is not directly defined, but is defined using an intermediate expression defined recursively so as to implement a search through pattern matching. In another form, one input terminal is specified, which is followed by a search for blocks having the terminal as an input node and the search for blocks having one of the output node strings as an input node recursively and cyclically until the output terminal is reached, so as to extract a string of nodes on which the signal is propagated. The system is provided with functions for recognizing and comprehending subsidiary structures of the circuit which are not defined by the entered net data. By the combinational use of the recognition result and the layout shape generating function prepared separately, the layout shape of the subsidiary structures are determined. Shapes of objects determined through the above process are laid out automatically, while avoiding obstacles, within a predetermined space. According to still another form, layout patterns of variable structure memorizing the object layout and wiring affair are prepared in advance, and a layout plan for a circuit having a hierarchical structure is created through the operation of embedding the circuit to be laid out into a pattern.

Method and system of circuit pattern understanding and layout

A semiconductor IC structure including a plurality of isolated devices in a single substrate of a first conductivity type comprising at least three wells of a second conductivity type formed in the substrate, two of the wells reaching different edges of a buried layer of the second conductivity type at the bottom of the substrate to define a first zone of the first conductivity type in the substrate and the other wells defining at least one second zone of the first conductivity type in the substrate, and a method of fabricating a semiconductor IC structure of the above-mentioned type.

Semiconductor IC structure including isolated devices in a single

A protective element for preventing electrostatic puncture of a semiconductor integrated circuit comprises a semiconductor substrate of one conductivity type, a first semiconductor region of the opposite conductivity type formed within a selected part of the surface of the semiconductor substrate, and a second semiconductor region of the one conductivity type formed within a selected part of the surface of the first semiconductor region, the first and second semiconductor regions being partially short-circuited. When a surge pulse voltage is impressed between the substrate and the second region, the element operates as a diode or a transistor so as to absorb the surge pulse.

Electrostatic puncture preventing element

A semiconductor device comprising at least a pair of NPN and PNP transistors is improved. This semiconductor device is characterized in that at least one pair of vertical transistors are formed in a semiconductor layer of the second conductivity type formed on a semiconductor substrate of the first conductivity type, the semiconductor layer of the second conductivity type serving as both the collector of one of the transistors and the base of the other and that the transistors are electrically insulated from each other by organic insulator formed on the inorganic insulating film on the semiconductor substrate. Thus, a semiconductor device can be obtained in which PNP transistors having good characteristics such as current amplification factor h.sub.FE and gain-bandwidth product f.sub.T are incorporated in an integrated circuit consisting mainly of NPN transistors.

Complementary semiconductor device

A method of manufacturing a semiconductor integrated circuit device, which includes at least one junction field-effect transistor and at least one bipolar transistor, is characterized in that a groove portion is formed by chemically etching a part of a diffused layer for the channel region of the junction field-effect transistor, and that a layer for the gate of the junction field-effect transistor having a conductivity type to opposite to that of the channel region is formed by diffusion in the diffused layer of the channel region beneath the groove portion, whereby the pinch-off voltage V.sub.p of the junction field-effect transistor is made as small as possible and is also made smaller than the base-emitter reverse withstand voltage V.sub.BEO of the bipolar transistor.

Method of manufacturing a semiconductor integrated circuit device which

A method of manufacturing a semiconductor integrated circuit device including N-P-N transistors is characterized in that a base region of at least one of the N-P-N transistors is partially etched and removed with chemicals, thus to be formed with a depression, and that an emitter region opposite in the conductivity type to the base region is formed in the base region beneath the depression, whereby the at least one N-P-N transistor is made higher in the current gain h.sub.FE than the other N-P-N transistors being the main constituents of the integrated circuit device.

Method of manufacturing a semiconductor integrated circuit device

In a capacitance circuit having a capacitance element which exhibits a breakdown characteristic and which generates noises at breakdown, the improvement comprising a constant-voltage element, which has a lower breakdown voltage than the capacitance element and a lower noise level than the capacitance element in the state of breakdown, connected in parallel with the capacitance element. The voltage across the capacitance element is clamped at the breakdown voltage of the constant-voltage element, so that the capacitance element is prevented from breaking down and thus generating noise components.

Capacitance circuit

A multiple transistor consists of vertical and lateral transistors, the collector region of the lateral transistor is formed by diffusion within the diffused base region of the vertical transistor simultaneously with the emitter region of the vertical transistor, into a structure in which the base of the vertical transistor and the collector of the lateral transistor are short-circuited. As a result the current gain of the lateral transistor can be varied by changing the area of the collector region.

Growing community of inventors

Kodaira, Japan

Noboru Horie