Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Noboru Egawa

Hitoshi Kokubun

Yasuhiro Fukuda

A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.

Semiconductor device having fuse and protection circuit

A method of manufacturing a mask ROM for storing quaternary data enables short turn around time, makes refining cell sizes simple, and enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two diffusion areas in accordance with quaternary write data. A current runs between these diffusion areas only when one of these two areas which is adjacent a gap is used as a drain. Accordingly, quaternary data can be read by a first reading when the first diffusion area is a source and the other diffusion area is a drain, and by reading a second reading when the first diffusion area is used as a drain and the other diffusion area as a source.

Method of manufacturing non-volatile read only memory

A method of manufacturing a mask ROM for storing quaternary data enables short turn around time, makes refining cell sizes simple, and enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two diffusion areas. Impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by a first reading when the first diffusion area is a source and the other diffusion area is a drain, and by reading a second reading when the first diffusion area is used as a drain and the other diffusion area as a source.

A read-only nonvolatile memory in which the leakage current of unselected memory cell transistors is suppressed. Adjacent memory cell transistors are commonly connected to drain lines, and adjacent memory cell transistors on the other side are commonly connected to source lines. Gates within a same row are commonly connected to a word line. An offset structure is formed on the drain side of each memory cell transistor, and a non-offset structure is formed on the source side. Accordingly, in each memory cell transistor a depletion layer is generated between the drain region and channel region when a drain line is activated, but the depletion layer directly under a drain region does not reach the channel region when the drain line is in a state of high impedance. Therefore, there is no leakage current from the drain to the source in unselected memory cell transistors. Since there is no leakage current flowing from unselected memory cell transistors to source lines, the read margin is enhanced.

Read-only nonvolatile memory

The mask ROM for storing quaternary data that enables a short turn around time, makes refining cell sizes simple, and that enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two n&plus; diffusion areas. n&plus; impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by reading once when one diffusion area is a source and the other diffusion area is a drain and by reading again when the first diffusion area is used as a drain and the other as a source.

Non-volatile read only memory and its manufacturing method

A semiconductor memory device capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption even when the quick chip enable access is made possible. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths are set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions. Further, a semiconductor memory device in another embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths are set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable signal and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

Semiconductor memory device

A semiconductor memory device capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption even when the quick chip enable access is made possible. the semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths am set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable signal and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions. Further, a semiconductor memory device in another embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths are set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable signal and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.

A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions. Further, a semiconductor memory device in another embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

An object of the present invention is to provide a semiconductor memory device capable of reducing a delay in the transmission of a chip select signal, which is developed inside a chip and providing very fast access times for chip selection. A chip select terminal to which a chip select signal is externally supplied, is electrically connected to an inner conductive pattern. A first input circuit is disposed as a pre-stage circuit so as to be electrically connected to each of a plurality of inner circuits. The chip select signal supplied to the chip select terminal from the outside of the chip is directly transmitted to each of the first input circuits through the inner conductive pattern so as to be supplied to each of the inner circuits.

A semiconductor integrated noise absorbing circuit comprising an output variation detecting circuit for detecting such a condition that the output signal level of an output buffer circuit changes from a high level to a low level, an input level detecting circuit for detecting such a condition that a voltage level in high level of an input signal line, a capacitor connected to the input signal line, and a gate circuit connected between the load capacitor and the signal line, the gate circuit being closed so as to connect the capacitor to the input signal line if the voltage level of the input signal line is high when the output level of the output buffer circuit changes from a high level to a low level.

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Tokyo, Japan

Noboru Egawa