Freescale Semiconductor,inc.

Noam Sheffer

Eran Glickman

Evgeni Ginzburg

Boaz Shahar

Erez Parnes

Shlomit Dorani

Liat Kochavi

Michal Shmueli

Adriano Leszkowicz

A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.

Method for performing plurality of bit operations and a device having plurality of bit operations capabilities

A method for transmitting data, the method includes scanning at least a first memory unit to retrieve data segments associated with multiple TDM channels, in response to a definition of multiple TDM time frames, each TDM time frame includes multiple time slots; sending the retrieved data segments to an array of line shifters; multiplexing data segments provided from the array of line shifters, in response to the definition, such as to provide in a parallel manner multiple data segments to multiple TDM lines; and transmitting a group of time division multiples data frames over a group of TDM lines.

Method for transmitting data and a device having data transmission capabilities

A method and a device for processing instructions based on register group size information includes a pipelined processor, an instruction memory unit and a register file, whereas the pipelined processor includes a write-back unit and an execution unit. The device is characterized by including a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction; and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information. The second register group size information and the second register identification information define a second group of target registers associated with a second instruction. The second instruction is provided to the pipelined processor before the first instruction.

Device and method for processing instructions based on masked register group size information

A device and method for processing information fragments, the method includes: receiving multiple information fragments from multiple communication paths; wherein the each information fragment is associated with a cyclic serial number indicating of a generation time of the information fragment; storing the multiple information fragments in multiple input queues, each input queue being associated with a communication path out of the multiple communication paths; determining whether at least one serial number associated with at least one valid information fragment positioned in a head of one of the multiple input queues is located within a pre-rollout serial number range; mapping, in response to the determination, serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues to at least one serial number range that differs from the pre-rollout serial number range; and sending to an output queue information fragment metadata associated with a minimal valued serial number out of the serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues.

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Tel Aviv, Israel

Noam Sheffer