International Business Machines Corporation

Noam Jungmann

Elazar Kachir

Israel A Wagner

Hezi Shalom

Donald W Plass

Lidar Herooti

Lior Binyamini

Lior Arie

Tomer Abraham Cohen

Rajiv V Joshi

James W Dawson

Yaron Freiman

Udi Nir

Haining S Yang

Dureseti Chidambarrao

Baozhen Li

Robert C Wong

Rouwaida N Kanj

Atsushi Ogino

Amira Rozenfeld

Omer Heymann

Limor Plotkin

Amit Amos Atias

Bishan He

Ehud Nir

Dana Bar-Niv

Uri Moshe

Doris Bittruf

Muhammad Suleiman

Yevgeniy Kuklin

Klimentiy Shimanovich

In an approach, a processor identifies a current cell depicted in an integrated circuit layout tool, the current cell of a hierarchical layout comprises a plurality of cells. A processor generates an overlay, the overlay comprising an abstraction of at least one object present in a higher level of the hierarchical layout that overlaps with the current cell. A processor projects the overlay onto the current cell.

Hierarchy-aware integrated circuit layout design

A method, system and product including adapting a value of a delay parameter that is utilized in an operation of a memory-cell array, wherein the delay parameter influences a ratio between an operation portion of a clock cycle and a pre-charge portion of the clock cycle, wherein writing or reading to the memory-cell array is enabled during the operation portion of the clock cycle and is disabled during the pre-charge portion of the clock cycle, wherein said adapting comprises: initializing the delay parameter with an initial value; writing a first test data into the memory-cell array; attempting to read from the memory-cell array a second test data; comparing the first test data with the second test data; and selecting a target value for the delay parameter based on said comparing.

Adaptive SRAM memory control

An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.

Short circuit detection in a read/write assist capacitor of a memory

A clock gating method and circuit for avoiding out-of-spec clock operations. The circuit comprises a clock gating section that gates a clock signal according to an enabling signal generated by an enabling signal controller, the enabling signal controller generating the enabling signal according to a set signal and a reset signal. The circuit further comprises a set signal generator that generates the set signal, a reset signal generator that generates the reset signal, and a feedback section that uses the enabling signal to generate the feedback signal for the reset signal generator. The reset signal generator generates the reset signal by using the feedback signal. The enabling signal controller further generates an acknowledgement signal having a high signal during a blocking period when the clock signal is blocked and utilizes the acknowledgement signal as an announcement to a higher circuit that the clock signal is blocked.

Clock gating circuit for avoiding out-of-spec clock operations in self-timed circuits

A system, program product, and method for processing synchronized memory repairs. The method includes identifying a faulty memory row from a plurality of functioning memory rows in a memory array. The method also includes executing memory row repair operations directed toward the faulty memory row and identifying a repair row to operationally replace the faulty memory row. The method also includes creating a multiple hot state within a memory decoder. The memory decoder includes logic circuitry for executing operation of the plurality of functioning memory rows. The method further includes activating a wordline of the identified repair row through the multiple hot state, and executing one or more memory operations on the identified repair row though the memory decoder. Accordingly, the embodiments disclosed herein facilitate synchronization of the repair row and functioning memory rows within the memory array, as well as any associated peripheral signals.

Synchronized memory repair system (SRS)

An approach for detecting potential failures and sensitivities, based on preliminary verification of timing circuits which includes feedback and combinatorial loops for is disclosed. The approach comprises relating timing events by algebraic equations, breaking loops, and feedbacks by backward reference, and then propagate signals through time and netlist.

Analysis of signal transitions in feedback circuits

An example computer-implemented method includes receiving hardware testing results, an address, input/output (I/O) data, a redundancy status, and an input-memory-output mapping corresponding to a memory being tested. The method includes locating a failed cell of the memory based on the hardware testing results, the address, the input/output data, the redundancy status, and the input-memory-output mapping. The method also includes automatically repairing the failed cell.

Locating failures in memory with redundancy

A memory array is described herein that includes a static random-access memory (SRAM) array to store data. The memory array also includes a bit circuit to retrieve the data from the SRAM array, the bit circuit to be operated with a clock signal that oscillates between a low state and an intermediate state, wherein the intermediate state is between the low state and a high state. Furthermore, the memory array includes a sense amplifier to amplify an output signal from the bit circuit indicating a value of the stored data, wherein the sense amplifier does not include a cross coupled positive field-effect transistor.

Memory array with reduced circuitry

A dynamic capacitor circuit having a first passive capacitor, a second passive capacitor, a first terminal of the first passive capacitor and a first terminal of the second passive capacitor connected together to receive an input signal through a resistor. The input signal includes a noise signal component. An alternating current (AC) coupled inverting amplifier has an input connecting a second terminal of the second passive capacitor, the second capacitor coupling the input signal to the AC coupled inverting amplifier input. A conductive path couples an output of the AC coupled inverting amplifier to a second terminal of the first passive capacitor to balance out any noise signal component of the input AC signal at the connection. The dynamic capacitor achieves an amount of noise reduction in a reduced space without applying deep trench capacitors (DTCAP) where the DTCAP is a capacitance formed in a plane perpendicular to the substrate.

Area-efficient dynamic capacitor circuit for noise reduction in VLSI circuits

A voltage-controlled delay line including a clipper configured to produce a clipped input voltage from an input voltage, an oscillator configured to produce a strobe pulse train that is initiated by the clipped input voltage, and a divider module configured to divide the strobe pulse train and produce an output voltage from the divided strobe pulse train.

Self-timed, log-space, voltage-controlled delay line

A method in a computer-aided design system for generating a functional design model of a static random access memory is described herein. The method comprises generating a functional representation of a first local evaluation logic coupled to a first set of consecutive global bit lines (GBLs) and a first set of local bit lines (LBLs), the first local evaluation logic comprising a plurality of devices. The method further comprises generating a functional representation of a second local evaluation logic communicatively coupled to the first local evaluation logic via the devices; the second local evaluation logic is coupled to a second set of consecutive GBLs and a second set of LBLs. In addition, the second set of consecutive GBLs consecutive to the first set of consecutive GBLs, the first and second evaluation logics to generate signals from the LBLs such that one GBL is to be active at any point in a read or write cycle and the other GBLs are not concurrently active.

Structure for static random access memory

A design structure can include elements that, when processed in a semiconductor manufacturing facility, produce an SRAM that includes a first local evaluator coupled to a first global bit line (GBL) and a first set of local bit lines (LBLs). The SRAM can also include a second local evaluator communicatively coupled to the first local evaluator. The second local evaluator is coupled to a second GBL and second set of LBLs. The second GBL is consecutive to the first GBL. The first and second evaluators are to generate signals from the LBLs such that one GBL of a combined first and second GBLs is active at any point in a read or write cycle.

A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability

A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold. The method further comprises that in response to said connecting, the supply selector of the circuit is invoked and disconnects one power supply from the memory element; whereby stress testing the circuit, the stress testing tests the memory element without a voltage difference condition, the stress testing tests the another element with the voltage difference condition.

Voltage comparator circuit and usage thereof

A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator.

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Tel Aviv, Israel

Noam Jungmann