Sony Semiconductor Solutions Corporation

Tower Semiconductor Ltd.

Sony Corporation

Matsushita Electric Industrial Co., Ltd.

Noam Eshel

Golan Zeituni

Thomas Ayers

Brian R Carey

Jinsuk Kang

Yosuke Ueno

Frederick T Brady

Yusuke Ikeda

Kiyoshi Makigawa

Zvika Lupu

Amit Sokolover

Yasuhiro Tomita

Yasunori Tsukuda

Kouji Matsuura

Hitoshi Suwa

Manabu Komiya

Jeffrey Allan Jacob

Tamas Toth

Avi Parvin

Fred Brady

It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.

Solid-state image sensor and imaging device

An image sensor and electronic apparatus comprise a pixel circuit configured to generate an analog signal; a vertical signal line configured to convey the analog signal from the pixel circuit; an analog amplifier circuit configured to receive the analog signal via the vertical signal line and generate an amplified signal; and a tail current boost circuit configured to modify an instantaneous gain bandwidth product of the analog amplifier circuit by temporarily modifying a tail current of the analog amplifier circuit.

Tail current boost circuit

The present disclosure relates to an imaging device and an electronic device capable of restricting an occurrence of a sunspot phenomenon in a simple configuration. The imaging device includes a sample/hold part that samples and holds a reset voltage as a reset level voltage of a pixel signal and an AD conversion part that analog digital (AD) converts the pixel signal, in which the AD conversion part selects and outputs one of a first output signal as the AD converted pixel signal and a second output signal at a predetermined level on the basis of a comparison result between the reset voltage held by the sample/hold part and a predetermined reference voltage. The technology according to the present disclosure can be applied to a CMOS image sensor, for example.

Imaging device and electronic device

An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.

Image sensor and electronic device with active reset circuit, and method of operating the same

A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.

Sample-and-hold circuit with RTS noise reduction by periodic mode switching

The present technology is concerned with a solid-state imaging device, a method of driving a solid-state imaging device, and an electronic device which are capable of reducing power supply noise of a pixel signal with a single-ended circuit arrangement. The solid-state imaging device includes a pixel section including a plurality of unit pixels disposed for photoelectric transduction, a power supply noise detector detecting a noise component from a power supply used to energize the unit pixels and outputting a single-ended canceling signal including a canceling component for canceling the noise component, a sample and hold section configured to sample single-ended pixel signals output from the unit pixels and hold and output pixel signals representing the sampled pixel signals from which the noise component has been removed on the basis of the canceling signal, and an A/D converter performing A/D conversion on the pixel signals that have been held. The present technology is applicable to a CMOS image sensor, for example.

Solid-state imaging device, method of driving solid-state imaging device, and electronic device

A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.

Sample-and-hold circuit with feedback and noise integration

An image processing circuit includes a first dual sample-and-hold circuit that samples a first data and a second data from a first pixel, a second dual sample-and-hold circuit that samples a third data and a fourth data from a second pixel, a voltage-to-current circuit including a resistor and a current source, that receives the first data and the second data to output a first difference data, and that receives the third data and the fourth data to output a second difference data; and an analog-to-digital converter that converts the first and second difference data from an analog form to a digital form.

Dual sample-and-hold circuit with resistive gain

A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is V+V+V+V, where Vis a threshold voltage of the first transistor, Vis a saturation voltage of the first transistor, Vis a threshold voltage of the second transistor, and Vis a saturation voltage of the second transistor.

Charge injection noise reduction in sample-and-hold circuit

A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.

State machine controlled MOS linear resistor

An image processing circuit comprises a first sample-and-hold circuit that samples a first data from a pixel; a second sample-and-hold circuit that samples a second data from the pixel; a voltage-to-current circuit that includes a resistor and a current source, and receives the first data and the second data to output a difference data; and a black sun spot determination circuit. The black sun spot determination circuit compares a first VSL level at a first time with a second VSL level at a second time, both from the second sample-and-hold circuit, and determines the presence of a black sun spot based on a difference between the first and second level.

Sample-and-hold circuit with black sun control

A sample-and-hold circuit having an error correction circuit portion that compensates for charge injection and noise. The error correction circuit portion includes an error-current-accumulating capacitor and a feedback circuit. The error-correction circuit performs error correction during a sampling operation by accumulating, at the error-current-accumulating capacitor, an error current output from an amplifier of the sample-and-hold circuit, and then applying, via the feedback circuit, a voltage boost to an input of the amplifier. The magnitude of the voltage boost depends on a voltage of the error-current-accumulating capacitor, and on various design parameters of the components of the circuit. By appropriately setting the design parameters, the magnitude of the fed-back voltage boost can be made to cancel out error due to charge injection and noise.

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Pardesia, Israel

Noam Eshel