International Business Machines Corporation

Noah R Mendelsohn

Jaishankar Moothedath Menon

Michael Howard Hartung

James T Brady

Michael Anthony Ko

Damon W Finney

David R Nowlen

James Perchik

Joel M Gould

Donald J Lang

Paul W Hunter

Richard Francis Freitas

Alexander H Frey, Jr

Narasimhareddy L Annapareddy

Richard C Mosteller

Shin-Yuan Tzou

Thomas R Hancock

A procedure controls execution of priority ordered tasks in a multi-nodel data processing system. The data processing system includes a node with a software-controlled processor and a hardware-configured queue-controller. The queue-controller includes a plurality of priority-ordered queues, each queue listing tasks having an assigned priority equal to a priority order assigned to the queue. The queue-controller responds to a processor generated order to queue a first task for execution, by performing a method which includes the steps of: listing said first task on a first queue having an assigned priority that is equal to a priority of said first task; if a second task is listed on a queue having a higher assigned priority, attempting execution of the second task before execution of the first task; if no tasks are listed on a queue having a higher assigned priority than said first queue, attempting execution of a first listed task in the first queue means; and upon completion of execution of the task or a stalling of execution of the task, attempting execution of a further task on the first queue only if another order has not been issued to place a task on a queue having a higher assigned priority. The method further handles chained subtasks by attempting execution of each subtask of a task in response to the processor generated order; and if execution of any subtask does not complete, attempting execution of another task in lieu of a subtask chained to the subtask that did not complete.

System and method for queuing of tasks in a multiprocessing system

An apparatus for dynamically allocating memory includes a processor, a free buffer pool memory and a control memory which stores control block data structures. The control block data structures enable a segmentation of the free buffer pool memory into a series of free buffer pools, each free buffer pool comprising plural identical size buffers, each succeeding free buffer pool including a larger buffer size than a preceding free buffer pool. A selection size parameter for a given free buffer pool is a value that is larger than the buffer size comprising the given free buffer pool, but less than a next larger buffer size in the next of the series of free buffer pools. A memory allocation procedure responds to a request from an executing procedure for allocation of buffer space by: (i) allocating a buffer from a free buffer pool memory whose associated selection size parameter is a next larger value than the buffer space that was requested; (ii) determining a difference between the allocated buffer size and the requested buffer space to find an unfulfilled amount of the requested buffer space; (iii) allocating a buffer from a free buffer pool memory whose selection size parameter is a next larger value, among selection size parameters, than the unfulfilled amount; and (iv) repeating ii and iii until the memory allocation procedure determines that there is no unfulfilled amount of the requested buffer space. The apparatus further includes 'quickcell' memory which is allocated without use of control block data structures.

Dynamic memory allocation that enalbes efficient use of buffer pool

A distributed data processing system includes a plurality of nodes interconnected by bidirectional communication links. Each node includes a control message line for handling of control messages and a control memory for storing the control messages. Each node further includes data message line for handling of data messages and a data memory for storing the data messages. A processor in the node causes the data message line to queue and dispatch data messages from the data memory and the control message line to queue and dispatch control messages from the control memory. Each node includes N bidirectional communication links enabling the node to have at least twice as much input/output bandwidth as the control message line and data message line, combined. An input/output switch includes a routing processor and is coupled between the N bidirectional communication links, the data message line and control message line. The input/output switch dispatches either a control message or a data message over at least one of the bidirectional communication links in accordance with an output from the routing control processor, thereby enabling each communication link to carry either data or control messages. If a communication link is busy with either a control or a data message, the routing control processor increments to another communication link to enable dispatch of a queued message.

Multi-node network with internode switching performed within processor

A computing system includes plural nodes that are connected by a communications network. Each node comprises a communications interface that enables an exchange of messages with other nodes. A ready queue is maintained in a node and includes plural message entries, each message entry indicating an output message control data structure. The node further includes memory for storing plural output message control data structures, each including one or more chained further monrtol data structures that define data comprising a message or a portion of a message that is to be dispatched. Control data structures that are chained from an output messsage control data structure exhibit a sequence dependincy. A processor is controlled by the ready queue and enables dispatch of portions of the message designated by an output message control data structure and associated further control structures. The processor prevents dispatch of one portion of a message prior to dispatch of another portion of the message upon which the first portion is dependent even if message transmissions are interrupted.

System and method using chained structure queues for ordering of message

A multiprocessor system includes a plurality of substantially identical nodes interconnected through a switching network, each node including a disk drive, NVRAM, and a processor. The system stores data in either a RAID or mirrored fashion across a plurality of disk drives in different nodes. When data is stored in a RAID arrangement, an NVRAM in a parity node is provided with an entry including the new data, a copy of old data from the node to which the new data is to be written, a copy of the old parity, and a synchronization state indicator. The parity node determines new parity and transmits the new data to the data node for storage. Upon receiving an acknowledgement, the parity node resets the synchronization indicator. When power-up occurs, after a power failure, the parity node scans its NVRAM for any entry and upon finding one with a non-reset state indicator, transmits the new data to a destination data node for entry thereby synchronizing the contents of data and parity nodes. In a mirrored system, NVRAM in only one node has a data identifier entered into its NVRAM so that, upon a power failure and subsequent power-up, that entry enables the system to know which disk drives are in a non-synchronized state, and to cause actions that result in re-synchronization.

Synchronization method for loosely coupled arrays of redundant disk

Apparatus is described for component replacement control in a data processing system, with each component being assigned a label that includes a component identifier and a replacement generation value. The apparatus includes a plurality of tables for redundantly storing replacement generation values for each component. The tables that store the replacement generation values are then updated to indicate the incremented replacement generation value for the new component. Circuitry then increments the replacement generation value assigned to a component identity that is replaced by a new component. The circuitry modifies the new component's label to indicate the incremented replacement generation value. When the system is subsequently started, the replacement generation values in each component's label are compared with the replacement generation values in the tables and wherever a match is not found, the component is rejected.

Component replacement control for fault-tolerant data processing system

A data processing system includes both volatile and nonvolatile memories, user-inaccessible file control software and performs a method for recovering from a malfunction occurring during a file transaction that prevents accomplished microscopic transactions from being lost. The method comprises the steps of: providing a log file to maintain a record of file transactions which may span both the volatile and nonvolatile memories; recording in the portion of the log file in volatile memory, old and new data images which result during a file transaction; writing the old and new data images to a portion of the log file which is contained in nonvolatile memory, with the new data image being written after it is certain that the old data image is present in the nonvolatile memory; and in the event of a malfunction, employing the log file in nonvolatile memory to determine the status of a file transaction and rolling back the transaction in the event the malfunction occurred prior to its completion, and further assuring that all file system actions have actually occurred for transactions marked as completed.

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Arlington, MA, United States of America

Noah R Mendelsohn