International Business Machines Corporation

Noah D Zamdmer

Steven H Voldman

James A Culp

Werner A Rausch

Jawahar P Nayak

Melanie J Sherony

Edward J Nowak

Brent A Anderson

Dureseti Chidambarrao

James David Strom

Grant Paul Kesselring

Edward P Maciejewski

Matthew S Angyal

Ishtiaq Ahsan

Erik S Unterborn

Varadarajan Vidya

A structure is provided that includes a first active circuit in which at least one of areas surrounding the first active circuit includes an active circuit-containing region. A second active circuit is spaced apart from the first active circuit. The second active circuit includes a circuit mimic fill area present in at least one of the areas surrounding the second active circuit. The circuit mimic fill area substantially matches the active circuit-containing region that is adjacent to the first active circuit. The circuit mimic fill area is located on an equivalent side of the second active circuit as the active circuit-containing region that is present adjacent the first active circuit. The use of the circuit mimic fill mitigates the effects over medium range and beyond distances that cause device failure.

Device mismatch mitigation for medium range and beyond distances

A circuit for determination of a resistance of an array of capacitive elements includes a reference ring oscillator circuit, the reference ring oscillator circuit being loaded with low-loss capacitive elements; an array test ring oscillator circuit, the array test ring oscillator circuit being loaded with the array of capacitive elements; and a resistance determination module, the resistance determination module configured to determine the resistance of the array of capacitive elements based on data from the reference ring oscillator circuit and the array test ring oscillator circuit.

Determination of series resistance of an array of capacitive elements

Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.

Process environment variation evaluation

A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including a non-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the non-silicided poly-silicon resistor. The dimensions of the non-silicided poly-silicon resistor are large enough so that the resistance of the non-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the non-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.

Determining thermal absorption using ring oscillator

A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

Halo-free non-rectifying contact on chip with halo source/drain diffusion

Growing community of inventors

Sleepy Hollow, NY, United States of America

Noah D Zamdmer