Skhynix Inc.

No Geun Joo

Jun Seok Noh

Byeong Yong Go

Sang Woo Yoon

A memory device includes a row-hammer tracking circuit configured to: generate short interval signals each having one of first to n-th lengths based on input intervals between active commands, and generate a rate control signal based on whether a pattern of the short interval signals corresponds to a row-hammer attack pattern; and a target command issue circuit configured to adjust a frequency of a target refresh operation according to the rate control signal.

Memory device including row-hammer tracking circuit and operating method thereof

An integrated circuit includes a sampling control circuit configured to generate a sampling enable signal by dividing a sampling period into a plurality of sub-sections according to an active counting signal generated by counting a number of inputs of an active signal during the sampling period, and comparing the active counting signal with a random signal for each sub-section; and a sampling circuit configured to sample and store an input address according to the sampling enable signal.

Integrated circuit and memory device including sampling circuit

A semiconductor device includes a peripheral circuit and a core circuit. The peripheral circuit enters a smart refresh mode in which a smart refresh operation is performed based on a command. The peripheral circuit generates a latch address signal from a target address signal to output the latch address signal through a global input/output (I/O) line in the smart refresh mode. The core circuit performs an adding operation and a subtracting operation of the latch address signal to generate first and second internal address signals. The core circuit performs the smart refresh operation for first and second banks based on the first and second internal address signals.

Semiconductor devices and refresh methods using the semiconductor devices

A semiconductor memory apparatus includes a plurality of memory banks and a refresh control circuit. The refresh control circuit, in each plurality of cycles, performs a refresh operation on at least one memory bank of the plurality of memory banks at a first refresh rate, and performs a refresh operation on the other memory banks of the plurality of memory banks at a second refresh rate. The refresh control circuit circulates the at least one memory bank on which the refresh operation is performed at the first refresh rate in each one or more cycles of the plurality of cycles.

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Icheon-si, South Korea

No Geun Joo