Xilinx, Inc.

Niyati Shah

Sabyasachi Das

Zhiyong Wang

Aaron Ng

Ruibing Lu

Xiaojian Yang

Frederic Revenu

Govinda Keshavdas

Implementing a partial reconfiguration design flow can include determining an interface net connecting static circuitry and a first reconfigurable module of a circuit design, performing, using a processor, a logical optimization on first circuitry of the static circuitry that is entirely external to the first reconfigurable module and on second circuitry entirely within the reconfigurable module, and excluding the interface net from processing using the logical optimization.

Logical and physical optimizations for partial reconfiguration design flow

Circuit design implementation can include selecting a first and second load each having a control pin of a same type driven by a different driver, determining whether the driver of the first load matches the driver of the second load, and modifying the circuit design to drive the control pins of the first load and the second load using the driver of the first load. Circuit design implementation can include selecting a net having a driver and a plurality of loads exceeding a threshold, determining a selected module of the circuit design having a number of the plurality of loads of the net that meet a cloning criteria, and, in response, modifying the circuit design by creating a clone of the driver within the selected module and driving each load of the net within the selected module with the clone of the driver.

Circuit design implementation using control-set based merging and module-based replication

A method of circuit design may include synthesizing a circuit design using a processor and, for the synthesized circuit design, selectively reducing, using the processor, fanout of nets having a number of loads exceeding a first threshold number of loads and having a selected netlist connectivity. The method may include placing the circuit design using a processor and, for the placed circuit design, selectively reducing, using the processor, fanout of nets according to at least one of a number of loads or criticality.

Fanout optimization to facilitate timing improvement in circuit designs

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San Jose, CA, United States of America

Niyati Shah