Dalsa Corporation

Nixon O

Eric Charles Fox

Gareth Pryce Weale

Simon Gareth Ingram

Suhail Agwani

A method includes a first step followed by a second step. The first step includes transferring photo charges in a delay register into a first readout register, transferring photo charges in a first storage register into the delay register, and transferring photo charges in a second storage register into a second readout register. The second step includes collecting photo charges in the first storage register, collecting photo charges in the second storage register, shifting photo charges in the first readout register toward a first output, and shifting photo charges in the second readout register toward a second output.

Sensor method for dual line integrating line scan sensor

A line scan sensor includes first and second rows of pixels, corresponding first and second readout registers, and a first clocking structure disposed between the first row of pixels and the first readout register. The first clocking structure includes a transfer gate electrode and a delay well electrode. In an alternative embodiment, a method includes a first step followed by a second step. The first step includes transferring photo charges in a delay register into a first readout register, transferring photo charges in a first storage register into the delay register, and transferring photo charges in a second storage register into the second readout register. The second step includes collecting photo charges in the first storage register, collecting photo charges in the second register, shifting photo charges in a first readout register toward a first out put, and shifting photo charges in a second readout register toward a second output.

Dual line integrating line scan sensor

A TDI sensor includes a column of pixels ordered from an initial pixel to a final pixel where each pixel includes reticulated clock conductors arranged to define a reticulation area and a pixel charge handling capacity. The reticulation area of a pixel increases from the final pixel to the initial pixel, and the pixel charge handling capacity increases from the initial pixel to the final pixel. The sensor includes a first bus structure of polysilicon, where the bus structure includes register element sets and each register element set includes a plurality of clock conductors. Each register element set includes a corresponding pixel reticulation area, and the pixel reticulation area of a first register element set is unequal to a pixel reticulation area of another register element set. The sensor also includes a second bus structure of metal disposed substantially diagonally to the first bus structure. The second bus structure includes clock bus sets, and each clock bus set includes bus conductors. A first bus conductor of a first clock bus set includes parallel segments, and each parallel segment is co-parallel to the first bus structure. A first clock conductor of each register element set extends in an elongate direction and defines a predetermined clock conductor length in a direction perpendicular to the elongate direction. The first clock conductor of each register element set includes a first bridge segment having a predetermined bridge segment length in the direction perpendicular to the elongate direction, the predetermined clock conductor length being greater than the predetermined bridge segment length. A first parallel segment of the first bus conductor of each clock bus set is disposed over the first bridge segment of the first clock conductor of a corresponding set of the plurality of register element sets and connected thereto with a contact.

Variable reticulation time delay and integrate sensor

A pixel includes five transistors, a pinned photodiode and a storage node. A first transistor is coupled between the pinned photodiode and the storage node. A second transistor is coupled between the storage node and an output drain voltage. A third transistor is coupled between the pinned photodiode and a pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

Pinned photodiode five transistor pixel

a pixel is formed in a substrate having a first conductivity type, the pixel being coupled to a register for output. The pixel includes a pixel channel of a second conductivity type formed in the substrate, a transfer gate electrode, a storage gate electrode and a photodiode. The pixel channel includes a transfer portion at a first end of the pixel channel proximal to the register, a diode portion at a second end distal to the register and a storage portion between the transfer portion and the diode portion. The transfer gate electrode is insulatively spaced over the transfer portion, and the storage gate electrode is insulatively spaced over the storage portion. The diode is formed within the diode portion using the storage gate electrode as a mask.

Pixel with buried channel spill well and transfer gate

A CCD sensor includes a readout register formed in substrate, the readout register including a channel, a bus structure and a connection structure. The bus structure includes plural spaced element sets, each element set including a first clock conductor. The first clock conductor of a first element set is a dual function conductor. The connection structure isolates the dual function conductor while coupling together the first clock conductor of each other set of the element sets. Alternatively, the sensor includes vertical and readout registers formed in a well in a substrate. The vertical register includes a vertical channel, a vertical bus structure and a vertical connection structure, and the readout register includes a readout channel, a readout bus structure and a readout connection structure. The readout bus structure includes plural spaced readout element sets, each readout element set including a first readout clock conductor. The first readout clock conductor of a first readout element set is a dual function readout clock conductor. The readout connection structure isolates the dual function readout clock conductor while coupling together the first readout clock conductor of each other set of the readout element sets. The vertical bus structure includes plural spaced vertical element sets, each vertical element set including a first vertical clock conductor. The first vertical clock conductor of a first vertical element set is a dual function vertical clock conductor. The vertical connection structure isolates the dual function vertical clock conductor while coupling together the first vertical clock conductor of each other set of the vertical element sets.

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Waterloo, Canada

Nixon O