Intel Corporation

Nivedha Krishnakumar

Barnes Cooper

Chia-Hung Sophia Kuo

Jaya L Jeyaseelan

Nadav Bonen

Toby Opferman

Vijay Bahirji

Virendra Vikramsinh Adsure

A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.

Memory power management method and apparatus

Growing community of inventors

San Diego, CA, United States of America

Nivedha Krishnakumar