Intel Corporation

Nivedha Krishnakumar

Rajeev D Muralidhar

Harinarayanan Seshadri

Youvedeep Singh

Suketu R Partiwala

Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

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Bengaluru, India

Nivedha Krishnakumar