Intel Corporation

Nitish Paliwal

David J Harriman

Rajesh M Sankaran

Kirk S Yap

Mahesh U Wagh

Mahesh S Natu

Raghunandan Makaram

Ioannis T Schoinas

Ishwar Agarwal

Peeyush Purohit

Archana Srinivasan

Ashish Gupta

Swadesh Choudhary

Pratik M Marolia

Mohan Nair

Manjula Peddireddy

Vijay Pothi Raj Govindaraj

Rahul Boyapati

Minjer Juan

A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.

Circuits and methods for coherent writing to host systems

In one embodiment, an apparatus includes: a transaction layer circuit to output transaction layer information; and a link layer circuit coupled to the transaction layer circuit, the link layer circuit to receive and process the transaction layer information and to output link layer information to a physical circuit. The link layer circuit may include a first selection circuit to receive and direct cache memory protocol traffic to a selected one of a first logical port and a second logical port. Other embodiments are described and claimed.

System, apparatus and method for handling multi-protocol traffic in data link layer circuitry

In one embodiment, an apparatus comprises: an endpoint circuit to perform an endpoint operation on behalf of a host processor; and an input/output circuit coupled to the endpoint circuit to receive telemetry information from the endpoint circuit, encode the telemetry information into a virtual bus encoding, place the virtual bus encoding into a payload field of a control message, and communicate the control message having the payload field including the virtual bus encoding to an upstream device. Other embodiments are described and claimed.

System, apparatus and method for communicating telemetry information via virtual bus encodings

Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

High bandwidth link layer for coherent messages

In one embodiment, an input/output port includes a stateful transmit port having: a history storage to store a value corresponding to a transmit on change field of a prior data packet; a comparator to compare a transmit on change field of the data packet to the value stored in the history storage; and a selection circuit to output the data packet without the transmit on change field when the transmit on change field of the data packet matches the value. Other embodiments are described and claimed.

System, apparatus and method for increasing efficiency of link communications

Growing community of inventors

Hillsboro, OR, United States of America

Nitish Paliwal