Freescale Semiconductor,inc.

Nitin Sharma

Terence L Johnson

Timothy R Miller

Phuong T Huynh

Ryan W Lobo

A circuit for adjusting a magnitude of a transmit signal includes a transmitter (), providing a transmit signal (). It also includes a transmitter amplifier (), receiving the transmit signal () and a power control adjustment signal (), and responsive thereto, providing an amplified transmit signal (). The circuit also includes a detector (), for detecting an amplitude of the amplified transmit signal (). Also included is an error component () for determining the difference between the amplitude and a reference level (). Further provided is a digital signal generator (), receiving the difference (), and responsive thereto, generating () a reference signal () and the power control adjustment signal (), where the reference level () is responsive to the reference signal ().

Power control feedback loop for adjusting a magnitude of an output signal

A method is provided for adjusting timing alignment in which a receiver generates a plurality of imbalanced correction codes (), and square waves both having the same frequency. The receiver mixes the imbalanced correction codes with the square waves to create a mixed signal (), and integrates the mixed signal over a correction code period to generate a signal power value (). The receiver adjusts a phase of the square wave in a first direction when the signal power value satisfies a first criterion (), and in a second direction when the signal power value satisfies a second criterion (). Each imbalanced correction code is symmetrical. And a total integrated value of one of the imbalanced correction codes over the correction code period is either above a first threshold, or below a second threshold, the first threshold being greater than or equal to the second threshold.

Circuit and method for adjusting timing alignment using programmable codes

A method is provided for reducing a DC bias in a receiver. This method includes isolating a second circuit portion from a first circuit portion () and determining a second DC bias correction value for the second circuit portion that will eliminate a second DC bias at the isolated second circuit portion (). The second circuit portion is then connected to the first circuit portion () and a bias-maximizing code word is generated at the first circuitry (). A first DC bias correction value is then determined that will eliminate a first DC bias at the first circuit portion (). The bias-maximizing code word is formed such that: a first integrated value of a first half of the bias-maximizing code word has a positive value, and a second integrated value of a second half of the bias-maximizing code word over half of the code word length has a negative value.

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Centreville, VA, United States of America

Nitin Sharma