Texas Instruments Corporation

Arm Limited

Other

Agere Systems Inc.

Nitin Kumar Agarwal

Aniruddha Roy

Anup Gangwar

Honnahuggi Harinath Venkata Naga Ambica Prasad

Ravishankar Sreedharan

Visvesvaraya Appala Pentakota

Rajavelu Thinakaran

Suresh Mallala

Venkata Ramanan R

Madhan Radhakrishnan

Preetham Narayana Reddy

Sachin Sudhir Turkewadikar

Narayana Sri Harsha Gade

Anand Hariraj Udupa

Kunal Suresh Karanjkar

Sumit Dubey

Sandeep Kesrimal Oswal

Venkat Ramakrishna Saripalli

Miles Paschini

Gautam Salil Nandi

Shakti Shankar Rath

Abhaya Kumar

Ramesh Kumar Singh

Vikas Kumar Sinha

Jagannathan Venkataraman

Rubin Ajit Parekhji

Neeraj Shrivastava

Brian Ashley Carpenter

Zheng Xu

Preetam Tadeparthy

Saurabh Singh

Vineet Mishra

Ravishankar S Ayyagari

Lakshmanan Balasubramanian

Venkata Ramanan

Samarth S Modi

Supreet Joshi

Dantes John

Michael Cronin

Nisha Patel

Mrityunjay Kr Baranwal

Visvesvararaya A Pentakota

Visvesvarya Pentakota

Visvesvarya Pentakota A

Nadeem Husain Tehsildar

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.

Enabling an external resistor for an oscillator

A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.

High quiescent current control

In one embodiment, a method of operating a computational system to evaluate a device under test, where the device under test is operable to receive a digital code input and output in response a corresponding output. The method injects a plurality of simulated faults into a pre-silicon model of the device under test. For each injected simulated fault, the method inputs a plurality of digital codes to the model. For each input digital code, the method selectively stores the input digital code if a difference, between a corresponding output for the input digital code and a no-fault output for the input, exceeds a predetermined threshold value.

Identifying defect sensitive codes for testing devices with input or output code

A computer-based method and system for synthesizing a Network-on-Chip (NoC) is provided. One method includes determining physical data, device data, bridge data, traffic data and domain data based on an input specification for the NoC; assigning a domain to each bridge port; partitioning each traffic flow into one of a plurality of bins based on the bridge port domain assignments and the domain crossing constraints; creating a virtual node at each bridge port endpoint; generating a candidate topology for each bin based on the physical data, the device data, the bridge data, the traffic data, the domain data and the virtual nodes, each candidate topology including bridge ports, a tree of routers, routes and connections; and generating a final topology by merging the candidate topologies.

Network-on-chip topology generation

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.

Switchover schemes for transition of oscillator from internal-resistor to external-resistor mode

A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

Multi-channel multiplexer

Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Precision oscillators that use imprecise components

A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.

Inductor detection

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

Low power operational amplifier trim offset circuitry

A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Slew boost circuit for an operational amplifier

In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Comparator low power response

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin on the chip, and where the pin is adapted to be coupled to an external resistor, where the external resistor is external to the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first switch, and a second capacitor coupled to a second switch. The oscillator circuit includes leakage circuitry coupled to the current mirror, where the leakage circuitry is configured to draw a current from the current mirror proportional to a leakage current flowing through the external resistor from circuitry internal to the chip.

Pin-leakage compensation scheme for external resistor-based oscillators

A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

Class AB buffer with multiple output stages

A method for facilitating the exchange of a stable cryptocurrency collateralized by government-issued debt. First granularity parameters are received through a first wallet interface of a first digital wallet. A first restricted use key is generated based upon the first granularity parameters and provided to an owner of a second digital wallet. A second restricted use key is generated based upon second granularity parameters received through a second wallet interface associated with the second digital wallet. Information from a blockchain wallet is accessed using the second restricted use key wherein the information relates to one or more of an ID classification and risk score of the second wallet owner at a level of detail determined by the second granularity parameters. An indication to proceed with a transaction between the first digital wallet and the second digital wallet may then be received through the first wallet interface.

Tokenized asset backed by government bonds and identity and risk scoring of associated token transactions

Growing community of inventors

Bengaluru, India

Nitin Kumar Agarwal