Apple Inc.

Nitin Bhargava

Brijesh Tripathi

Craig M Okruhlica

Guy Cote

Hao Chen

Joseph J Cheng

Timothy John Millet

Joseph P Bratt

James E Orr

Ching Elizabeth Ho

Syed F Ali

An apparatus includes a plurality of processor cores, a cache memory that includes a plurality of banks, and a power management circuit. The power management circuit is configured to maintain a power credit approach for the apparatus that includes tracking a total number of currently available power credits, and to store a plurality of threshold values. Each threshold value is associated with one or more of a plurality of throttling actions. In response to the total number of currently available power credits reaching a particular threshold value of the plurality of threshold values, the power management circuit performs the one or more throttling actions associated with the particular threshold value. The plurality of throttling actions includes selectively throttling one or more of the plurality of processor cores, and selectively throttling one or more of the plurality of banks in the cache memory.

Power throttling in a multicore system

A graphics processing circuit and method for power savings in the same is disclosed. In one embodiment, a graphics processing circuit includes a number of channels. The number of channels includes a number of color component channels that are each configured to process color components of pixel values of an incoming frame of graphics information. The number of channels also includes an alpha scaling channel configured to process alpha values (indicative of a level of transparency) for the incoming and/or outgoing frames. The graphics processing circuit also includes a control circuit. The control circuit is configured to place the alpha scaling channel into a low-power state responsive to determining that at least one of the incoming or outgoing frames does not include alpha values.

Alpha channel power savings in graphics unit

Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

Global configuration broadcast

An integrated circuit (IC) having a debug access port coupled to a processing circuit without a dedicated sideband interface is disclosed. In one embodiment, an IC includes a processor circuit and a DAP. The IC also includes a communications fabric over which communications transactions may be conveyed between the various functional circuits of the IC using a fabric protocol. Both the DAP and the processing circuit are coupled to the communications fabric. The IC also includes a translation circuit coupled between the processing circuit and the communications fabric. The translation circuit may translate transactions conveyed between the processing circuit and the DAP from or to a debug protocol to or from the fabric protocol. Thus, the DAP and the processing circuit may communicate according to the debug protocol without a dedicated sideband coupled therebetween.

Method and apparatus for connecting debug interface to processing circuits without sideband interface

A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.

Parallel hardware and software block processing pipelines

Methods and apparatuses for performing lossless normalization of input pixel component values. The apparatus includes a normalization unit for converting pixel values from a range of 0 to (2&#x2212;1) to a normalized range from 0.0 to 1.0. The step size between adjacent values of the normalized range is 1/(2&#x2212;1), and a maximum input value of (2&#x2212;1) corresponds to a normalized value of 1. The normalization unit divides each input pixel component value by (2&#x2212;1) in order to preserve the fidelity of the color information contained in the input pixel component value.

Pixel normalization

Methods and graphics processing pipelines for performing inline chroma downsampling of pixel data. The graphics processing pipeline includes a chroma downsampling unit for performing buffer-free downsampling of chroma pixel components. A vertical column of chroma pixel components is received in each clock cycle by the chroma downsampling unit, and downsampled chroma pixel components are generated on every clock cycle or every other clock cycle. Vertical, horizontal, and vertical and horizontal downsampling can be performed without buffers by the chroma downsampling unit. A programmable configuration register in the chroma downsampling unit determines the type of downsampling that is implemented.

Performing inline chroma downsampling with reduced power consumption

Methods and apparatus for performing an inline rotation of an image. The apparatus includes a rotation unit for reading pixels from a source image in an order based on a specified rotation to be performed. The source image is partitioned into multiple tiles, the tiles are processed based on where they will be located within the rotated image, and each tile is stored in a tile buffer. The target pixel addresses within a tile buffer are calculated and stored in a lookup table, and when the pixels are retrieved from the source image by the rotation unit, the lookup table is read to determine where to write the pixels within a corresponding tile buffer.

Inline image rotation

A display controller may include an RGB Interface module and a display port module, which may both use a target-master interface, in which the data receiving module pops pixels from the data sourcing module, and generates the HSync, VSync, and VBI timing signals. A dither module may be instantiated between the RGB interface module and display port module to perform dithering. The dither module may use a source-master interface, in which data signals and data valid signals are issued by the data sourcing module. In order to avoid having to use a large storage capacity FIFO with the dither module, a control unit may issue interface signals to the RGB Interface module and display port module, and clock-gate the dither module, to allow the data signals and data valid signals to properly interface with the RBG interface module and display port module, and provide data flow from the RGB interface module to the dither module to the display port module.

RGB-out dither interface

A parallel scaler unit for simultaneously scaling multiple pixels from a source image. The scaler unit includes multiple vertical scalers and multiple horizontal scalers. A column of pixels from the source image is presented to the vertical scalers, and each vertical scaler selects appropriate pixels from the column of pixels for scaling. Each vertical scaler scales the selected pixels in a vertical direction and then conveys the vertically scaled pixels to a corresponding horizontal scaler. Each horizontal scaler scales the received pixels in a horizontal direction.

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San Jose, CA, United States of America

Nitin Bhargava