Stmicroelectronics International N.v.

Stmicroelectronics Pvt. Ltd.

Synopsys, Inc.

Stmicroelectronics S.r.l.

Nitin Bansal

Saurabh Kumar Singh

Amit Katyal

Hemant Shukla

Massimiliano Picca

Rahul Gupta

Joshipura Jwalant

Kallol Chatterjee

Akhil Thotli

Rupesh Khare

Pratap Narayan Singh

Abhirup Lahiri

Ankit Agrawal

Sriram Kumar Jayanthi

SaurabhKumar Singh

Sayan Adhikary

Shrestha Bansal

Manoj Kumar Reddy Puli

A fail tolerant sensor circuit for adjusting an input signal received at an input pad to be provided to an integrated circuit (IC). The circuit includes a sensor input transistor including a first terminal coupled to the input pad, a second terminal coupled to a receiver circuit, and a gate. The circuit further includes a feedback loop that includes a first voltage clamp circuit having an input coupled to the second terminal of the senor input transistor and providing an output, and a first level shifter including an input coupled to the output of the first voltage clamp circuit and providing the feedback output coupled to the gate of the sensor input transistor.

Fail tolerant pad sensor circuit

A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, and PMOS clampers. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to generate limited voltage signals, each of which is a fraction of voltage between the pad and supply voltage or between the pad and ground. The NMOS clampers and PMOS clampers configured to receive reference voltages and limited voltage signals to generate output, which is in turn input into gate terminals of the subset of NMOS or PMOS transistors.

High-voltage IO drivers

A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.

Aging-resistant Schmitt receiver circuit

An input buffer circuit includes a tracking circuit that produces a tracking signal and an inverter including a cascade of low voltage switching devices coupled to an output of the tracking circuit. The tracking signal follows a first signal during a first time period and a second signal during a second time period. The tracking circuit is configured to reduce an input high voltage/input low voltage (VIH/VIL) spread.

Input Schmitt buffer operating at a high voltage using low voltage devices

A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor at varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.

Temperature sensing circuit with temperature coefficient estimation and compensation using time variable substrate heating

A digital low drop-out regulator circuit includes transistor switches that are selectively actuated in response to a comparison of an output voltage at an output node to corresponding tap reference voltages. A dynamic reference voltage correction circuit operates to shift voltage levels of the tap reference voltages in response to a difference between the output voltage at the output node and an input reference voltage.

Digital low drop-out (LDO) voltage regulator with analog-assisted dynamic reference correction

According to an embodiment, a voltage regulator includes a linear voltage regulator (LVR) and a transient feedback circuit. The LVR a primary feedback loop, an input terminal configured to receive an input voltage, and an output terminal configured to output a regulated voltage. The transient feedback circuit is coupled to the output terminal and the primary feedback loop, and is configured to provide a first current with a first polarity to the primary feedback loop when current flowing through the output terminal is increasing.

System and method for a linear voltage regulator

An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.

Circuit for regulating startup and operation voltage of an electronic device

A method and apparatus are provided. The apparatus includes a plurality of devices forming a positive feedback loop for driving a regulated output voltage towards a reference voltage. Device ratios of at least two of the plurality of devices are set such that the positive feedback loop is stable.

Voltage regulator

An FDSOI integrated circuit die supplies on an output node a regulated output voltage based on a reference voltage. A pass transistor that passes a first current to the output node. A feedback loop regulates the output voltage by generating a second current based on the first current and applying a control signal to the pass transistor based on the second current. A loop current adaptor adapts a ratio of the first and second currents by adjusting a back gate bias voltage applied to a back gate of loop transistor of the feedback loop.

Capless on chip voltage regulator using adaptive bulk bias

An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Area-efficient distributed device structure for integrated voltage regulators

The present disclosure teaches a power management device for providing one or more voltages and prohibiting the operation until the IC is initialized and voltage stability is achieved. The power management device includes a power regulator block and a masking block. The power regulator block includes one or more of the following elements:- a regulator, a bandgap reference generator, a low voltage detector LVDD, a low voltage detector LVDM, and a plurality of logic gates. In one embodiment, the masking block includes one or more level shifters, a plurality of logic gates, a D flip-flop, and a power on reset circuit (PoR).

On-chip power management

Described herein are principles for designing and operating a voltage regulator that will function stably and accurately without an external capacitance for all or a wide range of load circuits and characteristics of load circuits. In accordance with some of these principles, a voltage regulator is disclosed having multiple feedback loops, each responding to transients with different speeds, that operate in parallel to adjust an output current of the regulator in response to variations in the output current/voltage due to, for example, variations in a supply voltage and/or variations in a load current. In this way, a voltage regulator can respond quickly to variations in the output current/voltage and can avoid entering an unstable state.

A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.

Growing community of inventors

Gurgaon, India

Nitin Bansal