Stmicroelectronics Pvt. Ltd.

Infineon Technologies Austria Ag

Stmicroelectronics International N.v.

Stmicroelectronics (Crolles 2) Sas

Nitin Agarwal

Kallol Chatterjee

Nitin Kumar Gupta

Cheow Guan Lim

Pierre Dautriche

Mingping Mao

Dong Li

Weifu Yu

Guoxing Zhang

Jian-Wei Liu

Po-Jung Chung

Junaid Yousuf

A device for controlling a switching mode power supply includes a regulation module, a feedback node, and a resistance module. The regulation module is adapted to cause a switching module to selectively couple, based on an oscillation frequency, a primary side winding of a transformer and a supply to control a voltage, current, or power output at a secondary side winding of the transformer. The feedback node is adapted to receive an indication of a voltage at the secondary side winding of the transformer. The resistance module is adapted to selectively set a pull-up resistance based on a comparison between a time-controlled frequency and a voltage-controlled frequency that is generated based on a voltage at the feedback node, wherein the regulation module is adapted to set the oscillation frequency as the time-controlled frequency or the voltage-controlled frequency.

Adaptive control loop gain for switching mode power supply

In some examples, a controller device for a resonant mode power converter circuit comprises a feed-forward pin configured to receive an input voltage signal of the resonant mode power converter circuit, a feedback pin configured to receive an output voltage signal of the resonant mode power converter circuit, processing circuitry configured to determine a switching frequency based on the input voltage signal and the output voltage signal, a first control pin configured to deliver a first control signal to the first switch at the switching frequency, and a second control pin configured to deliver a second control signal the second switch at the switching frequency.

Controller device for resonant mode power converter circuit

In accordance with an embodiment, a method of operating a power supply includes detecting a loss of at least one of an AC input voltage an AC input power at an input of the power supply, and increasing a switching frequency of the power supply upon detection of the loss of the AC input voltage or AC input power.

System and method for detecting a loss of AC power in a switched-mode power supply

A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

System and method for variable frequency clock generation

A method and a circuit for measuring an on chip duty cycle. The circuit includes a capacitor, a switching circuit, a current source, a comparator circuit and a counter. The circuit receives a first clock signal and a second clock signal. The first clock signal has a 50% duty cycle and the second signal has an unknown duty cycle signal. The switching circuit first receives the first clock signal and then the second clock signal for measuring the duty cycle. The comparator circuit compares a comparator voltage with a reference voltage for the first clock signal to measure a first elapsed cycle using the counter. The comparator circuit again compares a comparator voltage with a reference voltage for the second clock signal to measure a second elapsed cycle using the counter. The counter measures the first elapsed cycle and the second elapsed cycle corresponding to the first clock signal and the second clock signal for a duration in which the comparator voltage equals the reference voltage. The duty cycle for the second clock signal is then calculated using the first elapsed cycle and the second elapsed cycle.

On chip duty cycle measurement module

A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.

Phase locked loop (PLL) method and architecture

A PWM generator system provides improved duty cycle resolution using a sub-cycle generator for generating a sub-cycle with a period that is a small fraction of the maximum PWM period to be generated. An integral sub-cycle estimator is coupled to said sub-cycle generator for determining the integral number of said sub-cycles for on and off time of the PWM waveform. An additional sub-cycle estimator determines the additional fractional sub-cycle required to provide the on and off time. A timer coupled to the integral sub cycle estimator and the additional sub cycle estimator controls PWM output switching for the on and off time of the integral and additional fractional sub cycles.

PWM generator providing improved duty cycle resolution

A phase locked loop (PLL) circuit includes circuitry for preventing an erroneous condition in charge pump operation. The PLL circuit is modified by adding delay elements for connection between the phase frequency detector and the charge pump. A digital logic circuit is also included to provide the clock signals for the loop filter wherein the clock signals have rising edges corresponding to an earlier occurring rising edge of either of the output signals from the phase-frequency detector.

Phase lock loop circuit with delaying phase frequency comparson output signals

A system and method generate a pulse width modulated signal having variable duty cycle resolution. A hardware uses minimal hardware to improve the PWM duty cycle resolution up to 0, such that highest possible resolution of a waveform can be obtained, including a sine wave. An embodiment of the invention uses a microcontroller, a divide by W counter, a delay circuit, a flip-flop, and a logic gate.

System and method for generating a pulse width modulated signal having variable duty cycle resolution

An improved on-chip voltage regulator providing improved reliability by eliminating voltage stresses on critical components, comprising, a reference-signal generating block providing a first-order temperature-compensated voltage-reference signal and a first-order temperature-compensated current-reference signal, an operational-amplifier block providing a regulated voltage, connected to the outputs of said reference signal generating block; a standby protection block receiving an external signal for enabling/disabling said reference-signal generating block and said operational-amplifier block, and; a protection voltage block connected to all said blocks; wherein critical elements of said blocks are connected such that voltage difference between any two terminals is always less than the break down voltage of said critical element.

On-chip voltage regulator

A method and system for generating variable frequency cyclic waveforms using pulse width modulation (PWM) to provide adjustable precision frequency and enhanced resolution is disclosed. The technique includes a plurality of sets of duty cycle values, each set corresponding to the desired waveform profile at a given frequency, coupled with a mechanism for applying a selected duty cycle for a variable number of PWM cycles, to achieve an adjustable fine resolution of the waveform frequency.

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Kanpur, India

Nitin Agarwal