Intel Corporation

Tahoe Research, Ltd.

Nitin A Deshpande

Omkar G Karhade

Debendra Mallik

Ravindranath Vithal Mahajan

Xiaoqian Li

Yoshihiro Tomita

Bassam Mohammed Ziadeh

Eric Jin Li

Sairam Agraharam

Edvin Cetegen

Mitul Bharat Modi

Mohit Bhatia

Shawna M Liff

John Stephen Guzek

Feras Eid

Christopher J Nelson

Adel A Elsherbini

Sandeep B Sane

Manish Dubey

Srinivas V Pietambaram

William J Lambert

Nachiket R Raravikar

Sabina J Houle

Robert M Nickerson

Tarek A Ibrahim

Christopher L Rumer

Bai Nie

Divya Pratap

Harikrishnan Ramanan

Johanna M Swan

Abhishek A Sharma

Aleksandar Aleksov

Sasha N Oster

Kemal Aygun

Robert Alan May

Islam A Salama

Sri Ranga Sai Boyapati

Sanka Ganesan

Wilfred Gomes

Brandon C Marin

Ram S Viswanath

Digvijay Ashokkumar Raorane

Leonel R Arana

Jeremy D Ecton

Gang Duan

Wei-Lun Kane Jen

Jorge A Sanchez

Rajendra C Dias

Steve S Cho

Yiqun Bai

Kinya Ichikawa

Charles A Gealer

Bharat P Penmecha

Aastha Uppal

Wesley Brook Morgan

Guotao Wang

Shankar Ganapathysubramanian

Tyler N Osborn

Jiro Kubota

Sagar Suthram

Lars D Skoglund

Aditya Sundoctor Vaidya

Tahir Ghani

Anand S Murthy

Sujit Sharan

Robert L Sankman

Chia-Pin Chiu

Kristof Darmawikarta

Rahul N Manepalli

Daoqiang Lu

James E Jaussi

Wei Ey Li

James Chris Matayabas, Jr

Je-Young Chang

Amruthavalli Pallavi Alur

Yikang Deng

Ravi V Mahajan

Sai Vadlamani

Hiroki Tanaka

Srikant Nekkanty

Zhimin Wan

Ling Liao

Gregorio R Murtagian

Amram Eitan

Christopher M Pelto

Andrew Alduino

Weihua Tang

Sri Chaitra J Chavali

Jason M Gamba

Susheel G Jadhav

Yosuke Kanaoka

Todd R Coons

Mohammad Enamul Kabir

Arnab Sarkar

Thomas J De Bonis

Shubhada H Sahasrabudhe

Kenneth Brown

Timothy A Gosselin

Malavarayan Sankarasubramanian

Haifa Hariri

Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

HBI die architecture with fiducial in street for no metal depopulation in active die

Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

Package architecture of photonic system with vertically stacked dies having planarized edges

Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

Package architecture of scalable compute wall having compute bricks with vertically stacked dies

Techniques and mechanisms for a reconstituted circuit device to be formed using a flow of material, by capillary action, in a region between a first die and a second die. In an embodiment, a rigid mass extends around, and between, the first die and the second die. The rigid mass comprises a first body of a first material, and a second body of second material, wherein the bodies each extend across the region to respective sidewall structures of the first and second dies. In the region, a portion of the first body forms a surface structure which adjoins the second body. A concave or convex shape of the surface structure is an artefact of a meniscus formed by the first material during a liquid state thereof. In another embodiment, the reconstituted circuit device further comprises an interconnect which adjoins, and extends through, the rigid mass.

Formation of a reconstituted circuit device using flow of a material by capillary action

Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Faraday rotator interconnect as a through-via configuration in a patch architecture

Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

Moisture seal coating of hybrid bonded stacked die package assembly

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Microelectronic structures including bridges

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Nested glass packaging architecture for hybrid electrical and optical communication devices

Disclosed herein are microelectronic structures including bridges, and related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate with first and second metal layers; a cavity in the substrate, where a portion of the first and second metal layers, are exposed with the portion of the first metal layer partially overlapping the portion of the second metal layer; and a bridge component in the cavity, having a first conductive contact at a first face and a second conductive contact at a second face opposing the first face, the second face towards a bottom surface of the cavity, the portion of the first metal layer is between the second face of the bridge component and the portion of the second metal layer, and the second conductive contact is electrically coupled to the portion of the second metal layer in the cavity.

Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

Edge-aligned template structure for integrated circuit packages

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active side and an opposing backside, and wherein the PIC is embedded in the insulating material with the active side facing down; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the backside of the PIC and the conductive pillar; and an optical component optically coupled to the active surface of the PIC.

Photonic integrated circuit packaging architectures

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

Embodiments described herein may be related to apparatuses, processes, and techniques for coupling a micro-lens array to a photonics die. In embodiments, this coupling may be performed as an attach at a wafer level. In embodiments, wafer level optical testing of the photonics die with the attached micro-lens array may be tested electrically and optically before the photonics die is assembled into a package, in various configurations. Other embodiments may be described and/or claimed.

Micro-lens array optically coupled with a photonics die

Embodiments disclosed herein include photonics packages. In an embodiment, a photonics package comprises a photonics die and a plurality of v-grooves on the photonics die. In an embodiment, a lens array is optically coupled to a spot size converter on the photonics die. In an embodiment, the lens array comprises a main body and a plurality of lenses extending out from the main body.

Enabling passive alignment for lens attach

Embodiments may relate to a microelectronic package that includes a substrate with a cavity therein. A component may be positioned within the substrate, and exposed by the cavity. A solder bump may be positioned within the cavity and coupled with the component, and a bridge die may be coupled with the solder bump. Other embodiments may be described or claimed.

Microelectronic package with substrate cavity for bridge-attach

Growing community of inventors

Chandler, AZ, United States of America

Nitin A Deshpande