Georgia Tech Research Corporation

Nitesh Kumbhat

Venkatesh V Sundaram

Rao R Tummala

Pulugurtha Markondeya Raj

Fuhan Liu

Xian Qin

Abhishek Choudhury

The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (&#x3bc;m). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

Interconnect structures and methods of making the same

Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.

Stress relieving second level interconnect structures and methods of making the same

The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

Interconnect assemblies and methods of making and using same

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

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Atlanta, GA, United States of America

Nitesh Kumbhat