Taiwan Semiconductor Manufacturing Comp. Ltd.

Nitesh Katta

Kuo-Nan Yang

Jerry Chang-Jui Kao

Chin-Shen Lin

Yi-Chuin Tsai

Chung-Hsing Wang

Chou-Kun Lin

Chien-Ju Chao

Chi-Yeh Yu

King-Ho Tam

A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a control signal. The control module is configured to generate the control signal and to determine a voltage level or a pulse width of the control signal in accordance with a current process corner condition of the voltage control circuits and at least one of first predetermined data and second predetermined data.

Post-silicon tuning in voltage control of semiconductor integrated circuits

In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.

Electromigration-aware layout generation

A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.

Power rail for preventing DC electromigration

In some embodiments, in a method, cell layouts of a plurality of cells are received. For each cell, a respective constraint that affects a geometry of an interconnect to be coupled to an output pin of the cell in a design layout is determined based on a geometry of the output pin of the cell in the cell layout.

A method for cell characterization with Miller capacitance includes characterizing input capacitance of an input of a first stage in a cell by considering a first current transition at the input of the first stage up to a first stop time. The first stop time occurs during the first current transition exhibits a substantial tail portion contributed by the later of a first input voltage transition and a first output voltage transition reaching a corresponding steady state voltage. The first input voltage transition is associated with the input of the first stage. The first output voltage transition is associated with an output of the first stage coupled to the input through a capacitor.

Cell characterization with Miller capacitance

A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit.

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Hsinchu, Taiwan

Nitesh Katta