Google Inc.

Leland Stanford Junior University

Sk Hynix Memory Solutions Inc.

Deepmind Technologies Limited

Nishant P Patil

Rama Krishna Govindaraju

Liqun Cheng

Xiang Zhou

Vincent Olivier Vanhoucke

Andrew Swing

Subhasish Mitra

Benoit Steiner

Matthew Sarett

Norman Paul Jouppi

Parthasarathy Ranganathan

Doe Hyun Yoon

David Lo

Pankaj Makhija

Haishan Zhu

Yingquan Wu

Chung Chun Wan

Meng-Kun Lee

Chenjie Gu

Derrick Preston Chu

Christopher Sigurd Fougner

Ching Yin Derek Pang

Cheng Chen

Nandan Sridhar

H-s Philip Wong

Prasanthi Relangi

Ching-Han Chiang

Hongzi Mao

Marisabel Guevara Hechtman

Daniel James Visentin

Charles Booth Schaff

Alejandro Ramirez Bellido

Jingning Han

Rene Andre Claus

Methods, systems, and apparatus, including an apparatus for generating clusters of building blocks of compute nodes using an optical network. In one aspect, a method includes receiving request data specifying requested compute nodes for a computing workload. The request data specifies a target n-dimensional arrangement of the compute nodes. A selection is made, from a superpod that includes a set of building blocks that each include an m-dimensional arrangement of compute nodes, a subset of the building blocks that, when combined, match the target n-dimensional arrangement specified by the request data. The set of building blocks are connected to an optical network that includes one or more optical circuit switches. A workload cluster of compute nodes that includes the subset of the building blocks is generated. The generating includes configuring, for each dimension of the workload cluster, respective routing data for the one or more optical circuit switches.

Reconfigurable computing pods using optical networks

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for encoding video comprising a sequence of video frames. In one aspect, a method comprises for one or more of the video frames: obtaining a feature embedding for the video frame; processing the feature embedding using a rate control machine learning model to generate a respective score for each of multiple quantization parameter values; selecting a quantization parameter value using the scores; determining a cumulative amount of data required to represent: (i) an encoded representation of the video frame and (ii) encoded representations of each preceding video frame; determining, based on the cumulative amount of data, that a feedback control criterion for the video frame is satisfied; updating the selected quantization parameter value; and processing the video frame using an encoding model to generate the encoded representation of the video frame.

Rate control machine learning models with feedback control for video encoding

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.

Asymmetric data communication for host-device interface

Methods, systems, and apparatus for updating machine learning models to improve locality are described. In one aspect, a method includes receiving data of a machine learning model. The data represents operations of the machine learning model and data dependencies between the operations. Data specifying characteristics of a memory hierarchy for a machine learning processor on which the machine learning model is going to be deployed is received. The memory hierarchy includes multiple memories at multiple memory levels for storing machine learning data used by the machine learning processor when performing machine learning computations using the machine learning model. An updated machine learning model is generated by modifying the operations and control dependencies of the machine learning model to account for the characteristics of the memory hierarchy. Machine learning computations are performed using the updated machine learning model.

Modifying machine learning models to improve locality

Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.

Bandwidth allocation in asymmetrical switch topologies

Methods, systems, and computer storage media storing instructions for managing processing system efficiency. One of the methods includes obtaining data splitting a plurality of general-purpose processing units in a processing system into a high-priority domain and a low-priority domain, wherein the general-purpose processing units in the high-priority domain are assigned to perform one or more tasks comprising one or more high-priority tasks, and the general-purpose processing units in the low-priority domain are assigned to perform one or more low-priority tasks; and during runtime of the processing system, obtaining memory usage measurements that characterize usage of system memory by the high-priority domain and the low-priority domain; and adjusting, based on the memory usage measurements, a configuration of (i) the high-priority domain, (ii) the low-priority domain, or (iii) both to adjust utilization of the system memory by the general-purpose processing units.

Managing processing system efficiency

The present disclosure relates to optimized matrix multiplication using vector multiplication of interleaved matrix values. Two matrices to be multiplied are organized into specially ordered vectors, which are multiplied together to produce a portion of a product matrix.

Optimized matrix multiplication using vector multiplication of interleaved matrix values

A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications. Further, three-dimensional CNFETs can be provided by utilizing the subject plasma exposure processes.

Multiple carbon nanotube transfer and its applications for making high-performance carbon nanotube field-effect transistor (CNFET), transparent electrodes, and three-dimensional integration of CNFETs

Growing community of inventors

Mountain View, CA, United States of America

Nishant P Patil