Senseeker Engineering, Inc.

Nishant Dhawan

Kenton T Veeder

Aaron Bluestone

Sean McCotter

Christoph Von Jutrzenka Trzebiatowski

The present disclosure provides a current generation circuit. In one aspect, the circuit includes a current source transistor and a current sink transistor connected to the current source transistor in series, with respective sources of the current source and sink transistors being connected with each other at a common node. A voltage difference between respective gates of the current source and sink transistors defines a current value flowing through the series, the voltage difference being variable such that the current value is either time-dependent or time-independent. Respective drains of the current source and sink transistors provide a high resistance output necessary to provide a current source or sink function thereby rejecting influence of drain variation or error on the current value.

Charge transfer circuit for compact modulators

The present disclosure provides an analog counter circuit for use in a minimal-sized circuitry. The analog counter circuit of the present disclosure can provide much higher resolution versus power consumption and layout area as compared to conventional digital counters. The analog counter circuit of the present disclosure can also provide much better bias supply management, step accuracy, multi-element step uniformity and lower supply spiking as compared to conventional analog counter architectures. The compact size of the disclosed counter circuit allows better integration of arrayed elements, such as, an array of image sensing pixels or an array of artificial neurons.

Dynamic resistance element analog counter

Methods and Systems for calibrating a Single Ramp Multiple Slope Analog to Digital Converter (SRMS ADC), the ADC including a counter and a plurality N of charge and discharge elements of different time constant i.e. slope, wherein the relationships between slopes is defined as a function of the shallowest slope Ssuch that S=K&#xb7;S, S=K&#xb7;S, . . . S=K&#xb7;Swhere the K values are integers, and the code count for conversion is C=K&#xb7;C+K&#xb7;C+ . . . K&#xb7;C+Cwhere each Crepresents an observed counts per each slope for a conversion, including; sampling for a first calibration pass a voltage with the ADC, discharging the voltage on the steepest slope for a number of counter counts C, charging and discharging on the remaining slopes up to Kto Kfor a number of counts per slope, Ce.g. Cto C, discharging the remaining voltage residue on the shallowest slope and note the count, C, sampling the same voltage on the ADC for a second calibration pass, discharging the voltage on the steepest slope for a modified number of counter counts C=C+/&#x2212;X, modifying the number of charge/discharge counts time Cfor the slopes Kto Kto adjust for the change expected from the modified steep slope discharge to reach the shallowest slope with the same expected residue as for the first calibration pass, discharging the remaining voltage residue on the shallowest slope and note the actual count, C, adjusting Kto Kbased on the difference between Cand C, and; using C=K&#xb7;C+K&#xb7;C+ . . . K&#xb7;C+Cas the count code for conversion.

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Santa Barbara, CA, United States of America

Nishant Dhawan