Nvidia Corporation

Inphi Corporation

Fujitsu Corporation

Hal Computer Systems, Inc.

Rambus Inc.

Samsung Electronics Co., Ltd.

S3 Incorporated, Inc.

Alliance Semiconductor Corporation

Tundra Semiconductor Corporation

Nirmal Raj Saxena

Sreenivas Krishnan

Philip Payman Shirvani

Richard Gavin Bramley

David T Wang

Shirish C Gadre

Lacky V Shah

Brian Matthew Fahs

Bryon S Nordquist

Eric T Anderson

Joel James McCormack

Peter C Mills

Michael Brendan Sullivan

Nick Barrow-Williams

Richard Reeve

Paritosh M Kulkarni

Mark Alan Overby

Andrew Currid

John Welsford Brooks

Prasad Modali

Chih-Wei David Chang

Saurabh Hukerikar

Javier Villagomez

John Stephen Montrym

Lawrence Tse

Christopher Haywood

Steven James Heinrich

Stephen William Keckler

Naveen Cherukuri

Wishwesh Anil Gandhi

Andrew J Burstein

Chao Xu

Paul Gyugyi

Dmitry Vyshetsky

Manan Patel

Liang Yin

Gentaro Hirota

Praveen Joginipally

Howard Tsai

Cyndi Jung

Vaishali Kulkarni

Adam Hendrickson

David Charles Patrick

Sandeep Navada

Eric Deshan McDonald

Hamid Reza Rategh

Sridhar Manthani

Anil Babu Nangunoori

Paul Racunas

Yiyang Feng

Bruce Cairns Moxon

Abhijeet Ghadge

Irving Michael Robinson

Victor Podlozhnyuk

Yanxiang Huang

David Wang

In various examples, motifs, watermarks, and/or signature inputs are applied to a deep neural network (DNN) to detect faults in underlying hardware and/or software executing the DNN. Information corresponding to the motifs, watermarks, and/or signatures may be compared to the outputs of the DNN generated using the motifs, watermarks and/or signatures. When a the accuracy of the predictions are below a threshold, or do not correspond to the expected predictions of the DNN, the hardware and/or software may be determined to have a fault—such as a transient, an intermittent, or a permanent fault. Where a fault is determined, portions of the system that rely on the computations of the DNN may be shut down, or redundant systems may be used in place of the primary system. Where no fault is determined, the computations of the DNN may be relied upon by the system.

Using neural networks to perform fault detection in autonomous driving applications

Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

Near-memory compute module

A memory device and a system that implements a single symbol correction, double symbol detection (SSC-DSD+) error correction scheme are provided. The scheme is implemented by calculating four syndrome symbols in accordance with a Reed-Solomon (RS) codeword; determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols; and generating an output based on a comparison of the three location bytes. The output may include: corrected data responsive to determining that the three location bytes match; an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match. A variant of the SSC-DSD+ decoder may be implemented using a carry-free subtraction operation to perform sanity checking.

Single-cycle byte correcting and multi-byte detecting error code

In various embodiments, a software program uses hardware features of a parallel processor to checkpoint a context associated with an execution of a software application on the parallel processor. The software program uses a preemption feature of the parallel processor to cause the parallel processor to stop executing instructions in accordance with the context. The software program then causes the parallel processor to collect state data associated with the context. After generating a checkpoint based on the state data, the software program causes the parallel processor to resume executing instructions in accordance with the context.

Techniques for recovering from errors when executing software applications on parallel processors

Apparatuses, systems, and techniques to decode encoded data. In at least one embodiment, parts of information for decoding the encoded data is provided to a plurality of processors, and parts of data decoded by the plurality of processors is combined.

Parity check decoding

Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Techniques for storing data to enhance recovery and detection of data corruption errors

Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

Error containment for enabling local checkpoint and recovery

Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.

Liveness as a factor to evaluate memory vulnerability to soft errors

In various examples, motifs, watermarks, and/or signature inputs are applied to a deep neural network (DNN) to detect faults in underlying hardware and/or software executing the DNN. Information corresponding to the motifs, watermarks, and/or signatures may be compared to the outputs of the DNN generated using the motifs, watermarks and/or signatures. When a the accuracy of the predictions are below a threshold, or do not correspond to the expected predictions of the DNN, the hardware and/or software may be determined to have a fault&#x2014;such as a transient, an intermittent, or a permanent fault. Where a fault is determined, portions of the system that rely on the computations of the DNN may be shut down, or redundant systems may be used in place of the primary system. Where no fault is determined, the computations of the DNN may be relied upon by the system.

In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.

Securing against errors in an error correcting code (ECC) implemented in an automotive system

Determining diagnostic coverage for memory using redundant execution

An autonomous driving system could create or exacerbate a hazardous driving situation due to incorrect machine learning, algorithm design, sensor limitations, environmental conditions or other factors. This technology presents solutions that use machine learning to detect when the autonomous driving system is in this state e.g., erratic or reckless driving and other behavior, in order to take remedial action to prevent a hazard such as a collision.

Detection of hazardous driving using machine learning

A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.

PCIE lane aggregation over a high speed link

Growing community of inventors

Los Altos Hills, CA, United States of America

Nirmal Raj Saxena