Qualcomm Incorporated

Nirav Narendra Desai

Venkata Biswanath Devarasetty

Sharath Kumar Nagilla

Darshan Kumar Nandanwar

Hithesh Hassan Lepaksha

Karthik Rangaraju

Venkatesh Ravipati

Lakshmi Narayana Panuku

Sravan Kumar Ambapuram

Nikhil Kumar Kansal

Kumar Kanti Ghosh

Shruti Hanumanthaiah

Shrikanth Shenoy

Sumit Gemini

Udayakumar Menon

Providing runtime power profile tuning based on eye state in processor-based Extended Reality (XR) devices is disclosed herein. In this regard, in some exemplary aspects, a processor of a processor-based XR device is configured to apply a default power profile, and detect, using an eye blink detection circuit, an eye close event of a user of the processor-based XR device. In response to detecting the eye close event, the processor selects a test power profile from a plurality of power profiles and applies the test power profile. The processor then measures an operating characteristic of the processor-based XR device and compares the operating characteristic with a corresponding reference range. Based on the comparing, the processor updates one or more power profiles of the plurality of power profiles.

Providing runtime power profile tuning based on eye state in processor-based extended reality (XR) devices

Systems, methods and computer-readable mediums may be used in portable computing devices (PCDs) for dynamically allocating system resources in a way that prevents or lessens degradation of power and performance KPIs while also avoiding temperature increases in the PCD that can create unpleasant user experiences. A smart resource allocation framework (SRAF) is triggered when a call is received or placed. Once triggered, the SRAF framework monitors a preselected set of state conditions to determine whether or not to place the wireless modem in a modem power-performance (Mod. Pow.-Perf) mode. If it determines that modem is to be placed in the Mod. Pow.-Perf. mode, a Mod. Pow.-Perf. process is performed dynamically allocates system resources and preferably also triggers a thermal framework that performs power reduction in one or more non-modem processing cores.

Smart resource allocation framework for dynamic allocation of system resources in personal computing devices (PCDs) that employ wireless modems

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

Performance aware partial cache collapse

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

Access optimized partial cache collapse

An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

Dynamic voltage selection for a single power rail in a multi-core domain

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Hyderabad Telangana, India

Nirav Narendra Desai