Intel Corporation

Niranjan Soundararajan

Sreenivas Subramoney

Ragavendra Natarajan

Saurabh Gupta

Shubhendu Sekhar Mukherjee

Lihu Rappoport

Jared Warner Stark, Iv

Rahul Pal

Arijit Biswas

Jayaram Bobba

Methods and apparatuses relating to instruction set architecture (ISA) based and automatic load tracking hardware for opportunistic re-steer of data-dependent flaky branches are described. In one embodiment, a processor includes a pipeline circuit comprising a decoder to decode instructions into decoded instructions and an execution circuit to execute the decoded instructions, a branch predictor circuit to generate a predicted path for a branch instruction, and a branch re-steer circuit to, for the branch instruction dependent on a result from a load instruction, check if an instruction received by the pipeline circuit is the load instruction, and when the instruction received by the pipeline circuit is the load instruction, check for a write back of the result from the load instruction between a decode of the branch instruction with the decoder and an execution of the branch instruction with the execution circuit, and when the predicted path differs from a path based on the result from the load instruction, re-steer the branch instruction in the pipeline circuit to the path and cause execution of the branch instruction for the path based on the result from the load instruction.

Instruction set architecture based and automatic load tracking for opportunistic re-steer of data-dependent flaky branches

In one embodiment, an apparatus includes a context-based prediction circuit to receive an instruction address for a branch instruction and a plurality of predictions associated with the branch instruction from a global prediction circuit. The context-based prediction circuit may include: a table having a plurality of entries each to store a context prediction value for a corresponding branch instruction; and a control circuit to generate, for the branch instruction, an index value to index into the table, the control circuit to generate the index value based at least in part on at least some of the plurality of predictions associated with the branch instruction and the instruction address for the branch instruction. Other embodiments are described and claimed.

System, apparatus and method for context-based override of history-based branch predictions

Technologies for dynamic acceleration of general-purpose code include a computing device having a general-purpose processor core and one or more hardware accelerators. The computing device identifies an acceleration candidate in an application that is targeted to the processor core. The acceleration candidate may be a long-running computation of the application. The computing device translates the acceleration candidate into a translated executable targeted to the hardware accelerator. The computing device determines whether to offload execution of the acceleration candidate and, if so, executes the translated executable with the hardware accelerator. The computing device may translate the acceleration candidate into multiple translated executables, each targeted to a different hardware accelerator. The computing device may select among the translated executables in response to determining to offload execution. The hardware accelerators may include, for example, a processor graphics, an image signal processor, or a field-programmable gate array. Other embodiments are described and claimed.

Technologies for dynamic acceleration of general-purpose code using binary translation targeted to hardware accelerators with runtime execution offload

Methods and apparatuses relating to dynamic asymmetric scaling of branch predictor tables are described. Branch predictor circuits to perform dynamic asymmetric scaling of branch predictor tables are also described. In one embodiment, a processor includes an execution unit to execute a branch instruction; and a branch predictor to generate a prediction for the branch instruction from either of a plurality of global history prediction tables of differing history lengths and a floating global history prediction table, wherein the branch predictor is to: for each of the plurality of global history prediction tables, track a total number of unique entries that provide a correct prediction which is not available in a global history prediction table of lower history length within a monitoring period that includes execution of a plurality of instances of the branch instruction, and assign the floating global history prediction table as an extension to a global history prediction table of the plurality of global history prediction tables having a greatest total number of unique useful entries in the monitoring period.

Apparatuses and methods for dynamic asymmetric scaling of branch predictor tables

In one embodiment, a branch prediction circuit includes: a first bimodal predictor having a first plurality of entries each to store first prediction information for a corresponding branch instruction; a global predictor having a plurality of global entries each to store global prediction information for a corresponding branch instruction; a second bimodal predictor having a second plurality of entries each to store second prediction information for a corresponding branch instruction; a monitoring table having a plurality of monitoring entries each to store a counter value based on the second prediction information for a corresponding branch instruction; and a control circuit to allocate a global entry within the global predictor based at least in part on the counter value of a monitoring entry of the monitoring table for a corresponding branch instruction. Other embodiments are described and claimed.

System, apparatus and method for controlling allocations into a branch prediction circuit of a processor

One embodiment provides an apparatus. The apparatus includes a store direct dependent (SDD) branch prediction circuitry and an SDD management circuitry. The store direct dependent (SDD) branch prediction circuitry is to store an SDD branch table. The SDD branch table is to store at least one record. Each record includes a branch instruction pointer (IP) field, a load IP field, a store IP field, a comparison info field and at least one of a store value field and/or a predicted outcome field. The SDD management circuitry is to populate the SDD branch table at runtime and to override a baseline branch prediction associated with an incoming branch IP with an SDD branch prediction, if the SDD branch table contains a first record populated with the incoming branch IP and at least one of a store value and/or an SDD predicted outcome.

Dynamic detection and prediction for store-dependent branches

In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.

Growing community of inventors

Santa Clara, CA, United States of America

Niranjan Soundararajan