Intel Corporation

Niranjan L Cooray

Altug Koker

Joydeep Ray

Abhishek R Appu

Ankur N Shah

Prasoonkumar Surti

Balaji Vembu

David M Puffer

Pattabhiraman K

Subramaniam M Maiyuran

Vasanth Ranganathan

Salvador Palanca

Angad Narang

Elmoustapha Ould-Ahmed-Vall

Varghese George

Lakshminarayanan Striramassarma

Rajesh M Sankaran

Kun Tian

Aravindh V Anantaraman

Vladimir M Pentkovski

Valentin Andrei

David J Cowperthwaite

Sameer Kp

Fernando Latorre

Vidhya Krishnan

Jaroslaw Topp

Satyeshwar Singh

Nicolas Kacevas

Murali Ramadoss

John H Feit

Hema Chand Nalluri

Saurabh Tangri

Varun Mohandru

Steve Tsai

Parth Damani

Satyanarayana Nekkalapu

Aditya Navale

Shekoufeh Qawami

Mike MacPherson

Stanislav Shwartsman

Josh B Mastronarde

Sungye Kim

Pratik M Marolia

Bryan R White

Pedro Lopez

William B Sadler

Ronald W Silvas

Steffen Kosinski

Sanjay Kumar

Sudhakar Kamma

Guadalupe J Garcia

Kritika Bala

Li-Gao Zei

Rami May

Madhura Joshi

David M Durham

Siddhartha Chhabra

Kamal Sinha

Uday R Savagaonkar

Carlos V Rozas

Naveen Neelakantam

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

Scott R Janus

Men Long

Ilan Pardo

Selvakumar Panneer

Jeffery S Boles

James A Valerio

Shlomo Raikin

Alaa R Alameldeen

Brent E Insko

Jayesh Gaur

Alpa T Narendra Trivedi

Arthur Hunter, Jr

Peter J Smith

David I Standring

Jagannath Keshava

Praveen B Mosur

Hsien-Hsin Lee

Chinnakrishnan S Ballapuram

Suresh N Kuttuva

Pritav Shah

Manuel A Aguilar Arreola

Thomas Gaertner

Steven D Pudar

Nicholas Kacevas

Tom Aviram-Rosenfeld

Jaroslav Topp

Steve Spangler

Asim Nisar

Margareth E Marrugo

Ethan Kalifon

Doron Gershon

Nicolas Galoppo Von Borries

K Pattabhiraman

Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.

Local memory translation table accessed and dirty flags

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.

Graphics processor data access and sharing

Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Scalable I/O virtualization interrupt and scheduling

Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

Multi-tile architecture for graphics operations

Assistance for hardware prefetch in cache access

An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

Apparatus and method for memory management in a graphics processing environment

An apparatus to facilitate memory data compression is disclosed. The apparatus includes a memory and having a plurality of banks to store main data and metadata associated with the main data and a memory management unit (MMU) coupled to the plurality of banks to perform a hash function to compute indices into virtual address locations in memory for the main data and the metadata and adjust the metadata virtual address locations to store each adjusted metadata virtual address location in a bank storing the associated main data.

Memory compression hashing mechanism

An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

Apparatus and method for efficient graphics virtualization

Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.

Control surface access using flat memory mapping

An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.

Interconnected systems fence mechanism

An apparatus and method for dynamic provisioning and traffic control on a memory fabric. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated set of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment; and a plurality of queues associated with each VM at different levels of a memory interconnection fabric, the queues for a first VM to store memory traffic for that VM at the different levels of the memory interconnection fabric; arbitration hardware logic coupled to the plurality of queues and distributed across the different levels of the memory interconnection fabric, the arbitration hardware logic to cause memory traffic to be blocked from one or more upstream queues of the first VM upon detecting that a downstream queue associated with the first VM is full or at a specified threshold.

Apparatus and method for dynamic provisioning, quality of service, and scheduling in a graphics processor

Growing community of inventors

Folsom, CA, United States of America

Niranjan L Cooray