Arizona State University

Niranjan Kulkarni

Sarma Vrudhula

Aykut Dengi

Jinghua Yang

Shimeng Yu

Joseph Davis

Nishant S Nukala

This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.

Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs

A sequential state element (SSE) is disclosed. In one embodiment, an SSE includes a differential sense flip flop (DSFF) and a completion detection circuit (CDC) operably associated with the DSFF. The DSFF is configured to generate a differential logical output. During a normal operational mode, the DSFF is synchronized by a clock signal to provide a differential logical output in a differential output state in accordance with a data input or in a precharge state based on the clock signal. The differential logical output is provided in a differential output state in accordance with a test input during a scan mode. The CDC is configured to generate a test enable input during the scan mode that indicates the scan mode once the differential logical output is in the differential output state. Accordingly, another SSE can be asynchronously triggered to operate in the scan mode without a separate scan clock.

Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuits

A differential sense flip flop (DSFF) that is named the Kulkarni Vrudhula flip flop (KVFF) is disclosed. In one embodiment, the DSFF includes a differential sense amplifier and an SR latch. The differential sense amplifier includes a first amplifier branch having a first output node, a second amplifier branch having a second, a first switchable discharge path, and a second switchable discharge path. The first switchable discharge path is closed to discharge the first output node when first output node is being discharged by the first amplifier branch and the second switchable discharge path is closed to discharge the second output node when second output node is being discharged by the second amplifier branch. This prevents the output nodes from floating and increases the reliability and robustness of the DSFF.

Energy efficient, robust differential mode d-flip-flop

A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

Method of obfuscating digital logic circuits using threshold voltage

A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions.

Robust, low power, reconfigurable threshold logic array

Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise.

Threshold logic element with stabilizing feedback

This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.

Threshold logic gates with resistive networks

Threshold gates and related circuitry are disclosed. In one embodiment, a threshold gate includes a threshold realization element and a magnetic tunnel junction (MTJ) element. The MTJ element is switchable from a first resistive state to a second resistive state. To realize a threshold function with the MTJ element, the threshold realization element is configured to switch the magnetic tunnel junction element from the first resistive state to the second resistive state in accordance with the threshold function. In this manner, the threshold gate may implement a threshold function that provides an output just like a complex Boolean function requiring several Boolean gates.

Threshold gate and threshold logic array

A method of mapping threshold gate cells into a Boolean network is disclosed. In one embodiment, cuts are enumerated within the Boolean network. Next, a subset of the cuts within the Boolean network that are threshold is identified. To minimize power, cuts in the subset of the cuts are selected.

Growing community of inventors

Tempe, AZ, United States of America

Niranjan Kulkarni