Virage Logic Corporation

Synopsys, Inc.

Niranjan Behera

Bruce L Prickett, Jr

Alexander Shubat

Yervant Zorian

Izak Kense

Harold Pilo

Deepak Sabharwal

Yong Zhang

Shreekanth Sampigethaya

Moon-Hae Son

Dharmesh Kumar Sonkar

A memory device includes a memory device and control circuitry. The memory array includes bitcells and bitlines connected to the bitcells. The bitcells are grouped into bitcell groups. The control circuitry is connected to the bitcell groups via the bitlines. The control circuitry adjusts connections with the bitcell groups to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations based on a half-word control signal being enabled.

Reduced circuit area memory device with a half-word memory architecture

An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.

Sequential delay enabler timer circuit for low voltage operation for SRAMs

A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.

Using sense amplifier as a write booster in memory operating with a large dual rail voltage supply differential

A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.

Systems and methods for reducing memory array leakage in high capacity memories by selective biasing

Improving statistical yield of a system-on-a-chip. The system-on-a-chip includes several memory systems. Each memory system includes a large number of memories. The memories are tested to identify any faulty memories. One or more margins of the faulty memories are then varied and the memories are then tested again.

Statistical yield of a system-on-a-chip

A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.

System and method for repairing a memory

A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.

System and method for testing a memory

A method and system for testing a multi-port memory cell are described. According to one embodiment of the invention, a multi-port memory device comprises an array of multi-port memory cells. Accordingly, each multi-port memory cell is connected to one word-line and two bit-lines per read/write port. The memory device includes memory testing logic to perform a first memory access operation (e.g., read/write) at a first port of the multi-port memory cell while the memory cell is in a stressed condition. For example, the first memory access operation occurs while a second memory access operation is emulated on a second port. Moreover, the memory access operations occur at a frequency that is substantially equivalent to a maximum operating frequency of the dual-port memory device.

Method and system for testing a dual-port memory at speed in a stressed environment

A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input circuit is coupled to the one or more defective memory columns.

Method and apparatus to reduce the amount of redundant memory column and fuses associated with a memory device

A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first group of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input-output circuit is coupled to the one or more defective memory columns.

Method and apparatus to change the amount of redundant memory column and fuses associated with a memory device

An apparatus and method in which a single fuse is asserted in a memory bank having a redundancy memory column structure. The assertion of the single fuse causes two or more of the input-output circuits to shift away from a primary memory column to a substitute memory column.

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Newark, CA, United States of America

Niranjan Behera