Seagate Technology Incorporated

Lsi Corporation

Niranjan Anant Pol

Rajesh Maruti Bhagwat

Hemant Vitthalrao Mane

Mark Ish

Jackson L Ellis

Nitin Satishchandra Kabra

Avinash Suresh Pisal

Ramesh C Tekumalla

Marc Timothy Jones

Jason Matthew Feist

Prakash Krishnamoorthy

Vineet Sreekumar

Jason Wayne Kinsey

Hemantkumar Vitthalrao Mane

Nahoosh Hemchandra Mandlik

A data storage system can have a hardware interposer connected inline between a plurality of controllers and a plurality of memories. A bus of the hardware interposer may be monitored with a security breach monitor of the hardware interposer to allow a deviation from a predetermined address range to be detected by the security breach monitor, which prompts the security breach monitor to block access through the hardware interposer for a first controller of the plurality of controllers.

No latency hardware interposer

An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.

On-chip NVM ISP emulation in FPGA

A data storage system employing distributed memories can have at least one host connected to a plurality of data storage devices via a network controller. One or more performance bottlenecks through the network controller may be identified with a performance module. A peer group consisting of at least two of the plurality of data storage devices is created with the performance module in response to the identified performance bottleneck so that a task can be assigned by the performance module to the peer group. The task may be chosen to mitigate the performance bottleneck by avoiding involvement of the network controller in the task.

Distributed data storage system with bottleneck mitigation

A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.

On demand configuration of FPGA interfaces

A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Hybrid storage device with three-level memory mapping

An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller.

Growing community of inventors

Pune, India

Niranjan Anant Pol