Zilog, Inc.

Niraj Kumar

Steven R Boyle

Hanumanthrao Nimishakavi

John Tran

Mazin Khurshid

Jean P Meunier

Ikuji Nobugaki

Ravi Narayanaswami

The technique takes advantage of the current ability to increase the density of electronic circuit elements on an integrated circuit chip by combining onto a single chip all of the circuit elements of two or more separate circuits, even when the masks of the separate circuits have been laid out with one or more different design rules, and then connect them to operate together. A mask layout database of one of the circuits at a time is globally changed, with the use of a standard computer software package, to conform it to the design rules of the mask layout database of another circuit, either before or after the circuit databases are combined into a single database.

Merging integrated circuit mask databases formed by different design

A two-step flash ADC includes a MSB reference ladder having a first plurality resistors of resistance r and a second plurality of resistors of resistance R, serially connected together on an alternating basis starting and ending with one of the first plurality of resistors. A LSB reference ladder having a total resistance R.sub.L is initially connected across a predetermined (2r+R) leg of the MSB reference ladder. The resistances r, R, and R.sub.L are selected such that the effective resistance resulting from connecting the LSB reference ladder in parallel with a (2r+R) leg of the MSB reference ladder is equal to a (r+R) leg of the MSB reference ladder. In a first step of the two-step flash ADC, MSB reference voltages are picked-off the MSB reference ladder from actual or effective (r+R) legs of the MSB reference ladder, compared against an analog input voltage, and used to generate the most-significant-bits of a digital number corresponding to the analog input voltage. In a second step of the two-step flash ADC, the LSB reference ladder is connected to a portion of the MSB reference ladder determined by the analog input voltage, LSB reference voltages are picked-off the LSB reference ladder from which the least-significant-bits of the digital number corresponding to the analog input voltage is generated. Carryover logic generates the digital number corresponding to the analog input voltage from the most-significant-bits and least-significant-bits thus generated.

Flash analog-to-digital converter

A semiconductor multi-device system incorporated on a single semiconductor chip is disclosed including a central processing unit, a bus, a plurality of peripherals, a plurality of on-chip data bus drivers connected to selected lines of the bus, and logic means for controlling the operation of the on-chip data bus drivers. The multi-device system of the invention is capable of interacting with off-chip components including an off-chip processing unit and off-chip peripherals. The off-chip components may also include a plurality of off-chip data bus drivers that drive data signals onto and off of an off-chip data bus. The on-chip and off-chip drivers must cooperate in order for data signals to transfer properly between the on-chip and off-chip components. The logic means of the invention is designed so as to minimize the logic necessary to cause the on-chip drivers and the off-chip drivers to cooperate properly. The logic means of the invention is also designed to function properly regardless of whether the on-chip processing unit or the off-chip processing unit is in control of the overall system comprising both on-chip and off-chip components. The logic means is also designed to control the operation of the on-chip drivers in a simple and efficient manner. Thus, a multi-device system is disclosed which is a significant improvement over those of the prior art.

Semiconductor multi-device system with logic means for controlling the

An existing integrated circuit layout is modified or revised in order to shrink it, update it, modify it for merger with another circuit on a single chip, or the like, in a manner which assures, prior to implementing the modified layout in an integrated circuit chip, that the electronic circuit implemented by it has not inadvertently been modified in the process. Data of the existing layout is first run on a net list extractor computer software program in order to determine its net list. After the layout is modified by usual computer techniques, the modified layout data is run on the extractor program to obtain another net list, and the net lists are then compared for any undesired differences. Once the modified layout has been determined to be free of any such differences, a set of masks are made from the modified database. The masks are used then used to manufacture the integrated circuit.

Technique for modifying an integrated circuit layout

Initial data and/or control bits of registers within a digital integrated circuit are simultaneously loaded from localized non-volatile memory cells provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.

IC chip having volatile memory cells simultaneously loaded with

Initial data and/or control bits of registers within a digital integrated circuit are loaded from a non-volatile and/or read-only memory provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.

System register initialization technique employing a non-volatile/read

A technique is disclosed for manufacturing an integrated circuit die which is capable of being packaged in any of two or more different package types having different arrangements of bonding posts. The circuit is laid out with redundant pads located at different places on the die so that one pad in each pair of redundant pads is accessible for bonding with posts in one package type, while the other pad in each pair of redundant pads is accessible for bonding with posts in another package type. Illustrative layouts are shown whereby various types of pads, e.g., power pads, signal input pads, signal output pads and bidirectional I/O pads, may be made redundant.

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Fremont, CA, United States of America

Niraj Kumar