Intel Corporation

Tahoe Research, Ltd.

Nir Rosenzweig

Efraim Rotem

Eliezer Weissmann

Doron Rajwan

Nadav Shulman

Yoni Aizik

Ankush Varma

Alexander Gendler

Krishnakanth Venkata Sistla

Esfir Natanzon

Hisham Abu Salah

Yevgeni Sabin

Alon Naveh

Guy M Therien

James G Hermerding, Ii

Jorge Pedro Rodriguez

Dorit Shapira

Tomer Ziv

Arik Gihon

Paul S Diefenbaugh

Eric DiStefano

Ashish V Choubal

Gal Leibovich

Jeffrey A Carlson

Ishmael F Santos

Ido Melamed

Nimrod Angel

Shay Levy

Zeev Sperber

Barnes Cooper

Avinash N Ananthakrishnan

Michael Mishaeli

Anand K Enamandram

Philip R Lehwalder

Hisham Abu-Salah

Yoav Ben-Raphael

Niv Tokman

Guy Satat

Amit Gabai

Evgeny Bolotin

Daniel Cartagena

Raanan Sade

Ohad Falik

Ron Gabor

Vivek Garg

Stanislav Shwartsman

Tod F Schiff

Igor Yanover

Ahmad Yasin

Alexander Uan-Zo-Li

Michael Zelikson

Shaun M Conrad

Tal Kuzi

Nikhil Gupta

Itai Feit

Ariel Szapiro

Jawad Haj-Yihia

Gavri Berger

Christopher J Lake

Adwait Purandare

Israel Hirsh

Lev Makovsky

Hem Doshi

Ameya Ambardekar

Elkana Korem

Eric Dehaemer

Arye Albahari

Nir Misgav

Chen Ranel

Daniel D Lederman

Vijay S R Degalahal

Tomer Weiner

David Pawlowski

Bart Plackle

Jeffrey Jull

Tamir Salus

Rachid Rayess

Assaf Ganor

Ruoying Ma

Natanel Abitan

Reena Patel

Vijay Degalahal

Maytal Toledano

James G Hermerding Ii

Benjamin J Gould

Rachid E Rayess

Levy Shay

In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

Processor having accelerated user responsiveness in constrained environment

Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

Current control for a multicore processor

A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

System, apparatus and method for loose lock-step redundancy power management

An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

Power management based on real time platform power sensing

Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

Application priority based power management for a computer device

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Device, method and system for transparently changing a frequency of an interconnect fabric

Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

Multi-level CPU high current protection

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

In one embodiment, an apparatus comprises: a plurality of intellectual property (IP) circuits, each of the plurality of IP circuits including a configuration register to store a dynamic current budget; and a power controller coupled to the plurality of IP circuits, the power controller including a dynamic current sharing control circuit to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits and generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.

System, apparatus and method for dynamically controlling current consumption of processing circuits of a processor

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Givat Ella, Israel

Nir Rosenzweig