Marvell International Limited

Intel Corporation

Marvellworld Trade Ltd.

Nir Paz

Mark Norman Fullerton

Oren Kedem

Ran Mor

Dror Markovich

Igor Brainman

Alon Pais

For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second. STA an Ack including a buffer capacity field including the capacity value.

Apparatus, system and method of communication during a transmit opportunity (TXOP)

For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second STA an Ack including a buffer capacity field including the capacity value.

Controlling a power supply which supplies a voltage to target circuit of an integrated circuit. An adjustable delay line powered by the supply voltage is co-located on the IC with the target circuit. The adjustable delay line is subjected to substantially the same operating conditions as the target circuit. A control unit measures a delay time of the adjustable delay line. Based on the measured delay time, the control unit outputs a control signal by which the power supply adjusts the supply voltage. The adjustable delay line comprises multiple distinct delay elements, each with delay properties and responsivity to changes in operating conditions. Each delay element emulates delay properties of physical elements (e.g., gates and wires) in the target circuit. In this manner, power consumption may be reduced, while still maintaining proper operation of the target circuit.

Closed loop voltage control using adjustable delay lines

Computer systems and methods for memory management in a computer system are provided. A computer system includes an integrated circuit, where the integrated circuit includes a processing unit and a memory controller coupled to the processing unit. The memory controller includes a first interface and a second interface configured to couple the memory controller with a first memory and a second memory, respectively. The second interface is separate from the first interface. The computer system includes the first memory of a first memory type coupled to the memory controller through the first interface. The computer system further includes the second memory coupled to the memory controller through the second interface, where the second memory is of a second memory type that has a different power consumption characteristic than that of the first memory type.

Computer system and method of memory management

A digital ring oscillator outputting a toggled clock signal. The clock signal is generated by a plurality of electronic cells that are arranged in series. At least one of the plurality of electronic cells receives a feedback of the clock signal. Control signals are received at an input for the plurality of electronic cells. Each electronic cell includes a first logic gate, a second logic gate, and an inverted logic gate coupled between the first logic gate and the second logic gate. For each electronic cell, a respective control signal controls whether an output signal received from the first logic gate of a preceding electronic cell is transferred through the first logic gate to the first logic gate in a succeeding electronic cell, or is inverted and transferred through the second logic gate to the second logic gate in a preceding electronic cell, based on the control signal.

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Azur, Israel

Nir Paz