Dialog Semiconductor Gmbh

Apple Inc.

Qimonda Ag

Dialog Semiconductor (UK) Limited

Nir Dahan

Shawn Searles

Vincent R Von Kaenel

Jay B Fletcher

Bo Yang

Hubert Attah

Olivier Girard

Karthik Manickam

Kevin Graham Allen

A voltage regulator circuit included in a computer system may generate a voltage level on a power supply signal using a source power supply signal and based initial values of one or more operation parameters derived from wafer-level test data. One or more operation characteristics of the voltage regulator circuit may be sampled, by a measurement circuit, at multiple time points to generated measurement data. A control circuit may adapt operation of the voltage regulator circuit based on the measurement data.

Computer system power monitoring

The present document relates to a digital counter providing counting information comprising at least a first and a second counting module, said counting modules being serially coupled forming a counting module chain; each counting module comprising at least a first and a second digital storage cell, each counting module providing module counting information comprising a width of at least two bits; the counting modules being adapted to change only one bit of said module counting information between two successive counting states; wherein the counting modules are coupled such that the start of counting of the second counting module is triggered by the first counting module if said first counting module once has passed through its possible counting states.

Digital counter comprising reduced transition density

An apparatus for synchronizing an incoming signal with a clock signal comprises two or more synchronizer circuits, wherein each synchronizer circuit receives the incoming signal and the clock signal. Each synchronizer circuit generates a synchronized signal, wherein the state of each synchronized signal changes on a different phase of said clock signal in response to a change of the state of said incoming signal. A decision mechanism circuit receives the synchronized signals generated by each synchronizer circuit, wherein the decision mechanism circuit determines the output signal in response to the change of the state of the incoming signal. The decision mechanism circuit further comprises a memory element having a state which is set according to a previously detected state of said signal, wherein the output signal is determined according to the state of the memory element.

Low latency synchronizer circuit

The present disclosure provides circuitry and a method for digital clock generation including the generation of integer and non-integer sub clocks. The proposed method provides simplified constant signal propagation and low skew in the divided clock path independent of division factor. Also provided is a simplified mechanism for generating low power clock patterns divided down by factors which are non-integer, phase-shifted, repeated pulse trains, dynamically changing and glitch-free.

Fully digital method for generating sub clock division and clock waves

A modular Gray code counter of arbitrary bit length having identical Gray code counter cells in every bit position. Each cell comprises a Toggle Flop and logic which triggers the Toggle Flop and sets the state of the Gray code counter cell. The two outputs of a cell feed two inputs of the next more significant cell. A parity flip-flop provides odd parity, and as a third input to the cell together with the other two inputs determines the state of the cell.

Modular low power gray code counter

Embodiments of the invention provide methods and apparatus for transferring information from a sender to a receiver, a symbol is selected out of a plurality of symbols representing the information, wherein each of the plurality of symbols representing the information comprises a number of digits, the number of digits equaling a number of parallel lines coupling the sender and the receiver. The digits of the selected symbol are sent from the sender to the receiver, wherein, via each of the number of lines, a signal representing one of the number of digits of the selected symbol is transferred. In the step of selecting a symbol, the symbol is selected such that the symbol differs from a lastly transferred symbol by one digit.

Growing community of inventors

Puchheim, Germany

Nir Dahan