Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nir Baruch

Amit Gur

Ori Goren

Roy M Shor

David W Todd

Nir Atzmon

Vinay Gupta

A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.

Memory management component having multiple memory management modules and method therefor

A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

Common public radio interface (CPRI) lane controller coupled to direct memory access (DMA) wherein a time division duplex (TDD) steers control of CPRI

A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.

System and method for data synchronization across digital device interfaces

Growing community of inventors

Tel Aviv, Israel

Nir Baruch