Advanced Micro Devices Corporation

Ati Technologies Ulc

Nippon HarshadKumar Raval

Philip Ng

Anthony Asaro

David A Kaplan

Anthony T Gutierrez

Paul Blinzer

Jeremy W Powell

Donald P Matthews, Jr

Millind Mittal

Leopold Grinberg

Samuel Richard Bayliss

A processor supports managing DMA accesses, in secure fashion, at an IOMMU. The IOMMU is configured to ensure that, for a given DMA request issued by an I/O device and associated with a particular executing VM, the device is bound to the VM according to a specified security registration process, and the request is targeted to a region of memory that has been assigned to the VM. The IOMMU thus prevents a malicious entity from accessing confidential information of a VM via DMA requests.

Secure direct memory access

In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.

Extended attributes for shared page tables

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Nippon HarshadKumar Raval