Advanced Micro Devices Corporation

Nipendra J Patel

Shyam G Garg

Basab Bandyopadhyay

James F Buller

Thomas E Spikes, Jr

Robert B Richart

A wafer surface cleaning method is provided comprising immersion of the wafer in a H.sub.2 O:NH.sub.4 OH:H.sub.2 O.sub.2 solution at a temperature less than 65.degree. C. prior to formation of a thin oxide such as a tunnel oxide or gate oxide. Immersion of the wafer in a sub-65.degree. C. NH.sub.4 OH results in a smoother wafer surface that increase the charge-to-breakdown (Q.sub.BD) of the subsequently formed oxide. In the tunnel oxide embodiment, the lower temperature solution also reduces the oxide etch rate of the solution enabling a minimum overgrowth of gate oxide which, in turn, enables the addition of an in situ growth temperature anneal of the gate oxide without altering other process parameters.

Wafer cleaning procedure useful in the manufacture of a non-volatile

A non-volatile memory device is provided having an array of single transistor memory cells read in accordance with an improved read cycle operation. That is, a selected cell mutually connected via a single bit line to other cells is assured activation necessary to discern a programmed or unprogrammed state of that cell. The non-selected cells connected to the selected cell are advantageously assured of non-activation by applying a negative voltage to the word lines associated with those cells. The negative voltage is less than the threshold voltage associated with the single transistor MOS device. The non-selected cells are thereby retained inactive to provide a singular active or inactive selected cell dependent solely upon the programmed state of the array. Negative voltage upon the non-selected cells provides minimal leakage of over-erased cells normally associated with depletion mode operation.

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Thorndale, TX, United States of America

Nipendra J Patel